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A new memory controller design to fix the 128K ROM space limitation of PCI architecture

IP.com Disclosure Number: IPCOM000126970D
Original Publication Date: 2005-Aug-16
Included in the Prior Art Database: 2005-Aug-16
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Abstract

PCI bus architecture allows adapter ROMs be allocated memory address range from C0000H to FFFFFh ( 256KB ) during boot up . However, not all of this 256KB is available for option ROMs as the system BIOS will typically use some if not all of the 0xE000-0xF000 range as seen with the IBM xSeries BIOS. Often BIOS is unable to allocate resources for ROM address space with large number of PCI adapters because the total memory space requirement exceeds 128K . On Xseries platforms this causes a 1801 error . This problem is somewhat alleviated by user following a boot order defined by trial and error method and by disabling adapter ROMs . This disclosure describes a mechanism to enable BIOS to successfully run option ROMs for many PCI adapters without these limitations

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A new memory controller design to fix the 128K ROM space limitation of PCI architecture

     The basic idea is that the memory controller will contain a segment register and will map address range in the C1000 to DFFFFh to physical memory located at an address defined as ( OPT_ROM_REMAP_TARGET + SLOT_NO * 128K )

     Physical address range C0000 to C0FFF is reserved for initialization code for each device .

     The benefit will be every PCI device will be able a maximum of 127K area without affecting other device and without any need for swapping memory content .

     This will allow unlimited number of ROM devices as long as any one does not need more than 127K , which is a very rare possibility .

     The memory controller will need to have at least following registers OPT_ROM_REMAP_CONTROL Memory controller uses the value of this register to translate the option ROM address space. This register should initialize to zero on power ON . A value of zero means Memory controller will not do any translation


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     OPT_ROM_REMAP_TARGET The value in this register defines the base address of target memory address

     OPT_ROM_REMAP_BASE The value on this register defines the Base address of the ROM space that is translated . This register should initialize to C1000

     OPT_ROM_REMAP_SIZE The value on this register defines the size of address of the ROM space that is translated . This register should initialize to 1EFFF

     The memory controller translates any address in the range from OPT_ROM_REMAP_BASE to ( OP...