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Method for an SSF-CSP with land-side capacitors, resistors, inductors, and stacked memory

IP.com Disclosure Number: IPCOM000126989D
Publication Date: 2005-Aug-16
Document File: 2 page(s) / 61K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a side-by-side folded flexible chip scale package (SSF-CSP) with land- side capacitors, resistors, inductors, and stacked memory. Benefits include improved functionality, improved performance, and improved ease of implementation.

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Method for an SSF-CSP with land-side capacitors, resistors, inductors, and stacked memory

Disclosed is a method for a side-by-side folded flexible chip scale package (SSF-CSP) with land- side capacitors, resistors, inductors, and stacked memory. Benefits include improved functionality, improved performance, and improved ease of implementation.

Background

      Several different types of conventional folded (flex) packages are in use. Many have one package for a logic die on a substrate. A flex substrate or tape is folded and another package is stacked on top. Capacitors or inductors can be embedded in the substrate or placed on a tape. Alternatively, capacitors or inductors can be mounted side by side with the logic or memory package. These solutions result in package height increases (see Figure 1).

      A solution is required that accommodates smaller form factors.

Description

      The disclosed method is two chip scale packages located side by side on the same flex substrate with land-side components and stacked memory.

              The key elements of the disclosed method include:

•             Two logic packages located side by side on same flex substrate

•             Land-side capacitors, resistors, and inductors

•             Logic packages that are stacked on top of each other with adhesive tape between them

•             One fold to the flex substrate

•             Memory that is stacked on top after the fold

•             Ball grid-array balls soldered to...