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Method for a variable-width 3-way addition instruction

IP.com Disclosure Number: IPCOM000127013D
Publication Date: 2005-Aug-17
Document File: 2 page(s) / 36K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a variable-width 3-way addition instruction. Benefits include improved functionality, improved performance, and improved power performance.

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Method for a variable-width 3-way addition instruction

Disclosed is a method for a variable-width 3-way addition instruction. Benefits include improved functionality, improved performance, and improved power performance.

General description

              The disclosed method assumes a pipeline with a 2-cycle pipelined execute stage, incorporating a 3:1 adder in both pipe stages. The instruction produces multiple flags in parallel into special registers.

              The disclosed method can be applied to data of any precision packed into any size data path, such as 8-bit data packed 16-bits wide into a 128-bit data path.

              The key elements of the disclosed method include:

•             Usage of the 3:1 adders to enable accumulation

•             Processing of packed data with a single instruction

•             Usage of an instruction in a VLIW and super-scalar processor without incurring dependencies through the special purpose registers

•             Usage of the specials purpose registers

•             Definition that can handle variable-width addition, such as 2, 4, 6 and 8-bits wide

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to performing wide 3-way additions

•             Improved performance due to providing significant savings in fetch, decode, rename and schedule bandwidth/energy expenditure

•             Improved power performance due to enabling the processing of packed data with a single instruction

Detailed description

              The disclosed method includes special control registers. Their use can be illustrated using an example of an instruction to compare result registers. The instruction is described in the context of a processing core having a super-scalar issue and/or a very long instruction word (VLIW) issue. The data type used in this example is packed 16-bit in 32-bit registers (or memory ports).         

              All the compare results generated every cycle are shifted into two shift-registers. If more than one instruction causing a shift to the result registers is issued in the same cycle, the result registers are shifted by the sum of the shift values of all instructions. All the instructions consuming the result registers conditionally shift them after reading out the relevant bits. All instructions modifying the registers shift them before the update.

              One compare result register is used for collecting flags generated by the first stage of execution, and for providing flags to the first execution stage. Another compare result register does the same function for the second execution stage. Adhering to that separation of labor in the definition of all instructions enables dispatching instructions to consume and produce these registers back-to-back in consecutive cycles.

              Instructions that update the compare resul...