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Method for hardware prefetching of the structured data of cache miss loads

IP.com Disclosure Number: IPCOM000127016D
Publication Date: 2005-Aug-17
Document File: 7 page(s) / 85K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for hardware prefetching of the structured data of cache miss loads. Benefits include improved functionality and improved performance.

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Method for hardware prefetching of the structured data of cache miss loads

Disclosed is a method for hardware prefetching of the structured data of cache miss loads. Benefits include improved functionality and improved performance.

Background

              Accessing data connected by linked pointers can often result in cache misses on each item in a structure. Prefetching is difficult because the address of a subsequent item is typically only available by accessing a pointer. This conventional solution serializes the cache misses, resulting in poor performance.

General description

              The disclosed method is hardware prefetching of the data of cache miss loads that exhibit spatial properties between items connected by a data structure. The purpose is to optimize data accesses.

              The method is based on the idea that related items can be prefetched without following pointers if the relative placement properties of the items, is known. The related cache lines can be prefetched in parallel with servicing the first data cache miss or sometime later, as determined by the prefetching engine. The result is that memory prefetching is more effective because processing time to access the next element in a pointer chain may not be available. Furthermore, the disclosed method is more general than stride prefetching, which is a special case of the method.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to performing hardware prefetching of the data of cache miss loads that exhibit spatial properties between items connected by a data structure

•             Improved functionality due to catching misses not captured by next-line prefetching

•             Improved functionality due to using TYPE information as a prefetch trigger

•             Improved functionality due to capturing long-range misses

•             Improved performance due to using only the cache miss information obtained from the second-level cache to trigger the data stream

•             Improved performance due to using type information in type-safe object-oriented language systems

•             Improved power performance due to eliminating the execution of not-useful prefetches

Detailed description

              The disclosed method includes a prefetching engine that interacts with an existing memory system (see Figure 1).

              The engine monitors the data cache misses of a particular cache, for example level-2 cache. The engine detects structured data from an initial load that is missing in the cache (delta stream). The engine generates a series of prefetches at appropriate times. The trigger for a particular series of prefetches is an instruction address. Each prefetch request for a particular cache line (address) is made sometime after the initial miss. A priority is associated with the request.

              Information about the data stream is stored in a table. For example, the table could contain four entries....