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Novel Process for Joining Semiconductor Chip to Laminate Substrate

IP.com Disclosure Number: IPCOM000127304D
Original Publication Date: 2005-Aug-22
Included in the Prior Art Database: 2005-Aug-22
Document File: 2 page(s) / 117K

Publishing Venue

IBM

Abstract

Novel process for joining semiconductor chip to laminate substrate.

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Novel Process for Joining Semiconductor Chip to Laminate Substrate

An increasing number of semiconductor applications are requiring low cost high performance packaging to laminate substrates. This type of package can be constructed using low temperature C4 interconnects. However, during the joining of the silicon chip to laminate substrate, the non-planer nature of the laminate at elevated temperature results in significant non-wets. Also, the difference in thermal expansion coefficients between the silicon chip and laminate substrate results in a highly stressed module package. Disclosed is a means of joining a C4 bumped silicon chip to a laminate substrate without heating the laminate during joining. By eliminating the heating of the laminate, the problems associated with the laminate distortion and expansion are eliminated. This can be accomplished with the use of infrared radiant heat localized to melt the solder during joining. The process sequence is illustrated in the cross section schematics shown below. Figure 1 illustrates the base plate or chuck assembly which would be constructed of a high thermal conduction material such as aluminum with a very flat surface. The laminate substrate is placed on the planer surface as shown in Figure 2, with contact pads facing up. A rigid thermal insulator, such as a machineable ceramic, with a reflective top surface, such as polished aluminum or gold, is placed over the laminate. As shown in Figure 3, the reflective rigid insulator is formed in such a way as to allow for the chip to protrude through openings while contacting the perimeter of the laminate substrate. The function of the rigid top plate is to keep the laminate substrate flat and in good contact with the underlying base plate. This assembly can be fabricated in an array as illustrated in Figure 7 to allow for the simultaneous joining of multiple chips. The C4 bumped silicon chip is placed into the opening of the thermal insulator with the C4s in contact with substrate pads as shown in Figure 4. The back surface of the silicon chip may either have a high emissivity metal layer or be topped with a high emissivity metal plate as illustrated in Figure 5. The assembly is placed into a reflow furnace and heated with infrared radiant heat from the top surface only, as shown in Figure 6 . The metal layer or plate on the chip absorbs the radiant energy resulting in an increase in temperature. The surface of the rigid thermal insulator reflects the incident radiant energy thereby minimizing the heating of the laminate substrate. Heat is conducted from the top metal layer or plate, through the silicon chip, then to the tips of the C4s. The temperature is raised above the melting temperature of the C4 solder allowing it to wet the contact pad of the laminate to form the interconnect. Another embodiment of this disclosure is to apply a solder paste to the substr...