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Method for a system clock failure watchdog circuit on network processors

IP.com Disclosure Number: IPCOM000127431D
Publication Date: 2005-Aug-30
Document File: 4 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a system clock failure watchdog circuit on network processors. Benefits include improved functionality, improved system availability, and improved reliability.

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Method for a system clock failure watchdog circuit on network processors

Disclosed is a method for a system clock failure watchdog circuit on network processors. Benefits include improved functionality, improved system availability, and improved reliability.

Background

              In conventional network processors, electrostatic discharge (ESD) can cause the sensitive internal phased-lock loop (PLL) and clock generator to transition to an unknown state, which can cause the system clock to fail.

              When the system clock stops, the internal watch-dog timer stops because it is regulated by the system clock. As a result, the watchdog timer cannot reset the processor and the processor halts until an external reset or power OFF/ON is applied.

General description

              The disclosed method is a system clock failure watchdog circuit.

              The key elements of the disclosed method include:

•             Ring oscillator

•             Edge detector

•             Watchdog timer

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to detecting a hardware failure (system clock down) rather than a software failure

•             Improved functionality due to enabling the watchdog circuit to function as long as power is supplied

•             Improved functionality due to providing a backup clock (failsafe clock) to the functional blocks in the processor during system clock failure for critical system management

•             Improved system availability due to enabling automatic device reset

•             Improved reliability due to being backed by two counters instead of one

Detailed description

              The disclosed method is a system clock failure watchdog circuit. It contains a ring oscillator that generates a free running clock that is independent of the PLL. The oscillator is disabled when power_on_reset_n is 0 (assertion of external reset during power up). The edge detector detects the rising edge of the system clock, as an indication that the system clock is active or inactive. The watchdog timer is comprised of two counters clocked by the ring oscillator clock. The counters increment from 0 to N and stops at N. They are asynchronously reset by the edge detector whenever there is a rising edge at the system clock. When they count to N, they trigger the assertion of the system_fail signal. Additionally, the two counters restart synchronously, reloaded with the value 0, anytime the counters have different count values due to flip-flop soft errors (see Figure 1).

              The watchdog timer component is a count-up timer that counts from 0 to N. During normal operation, the edge detector always senses a rising edge during each cycle of the system clock. The edge resets the watchdog timer counters, so they never reach the maximum value, N.

              If the system clock stops, no rising edge occurs. After some period, the counters reach the terminal count N, which tri...