Browse Prior Art Database

Method for a programmable delay flip-flop network

IP.com Disclosure Number: IPCOM000127434D
Publication Date: 2005-Aug-30
Document File: 4 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a programmable delay flip-flop network. Benefits include improved functionality, improved power performance, improved yield, and an improved development environment.

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Method for a programmable delay flip-flop network

Disclosed is a method for a programmable delay flip-flop network. Benefits include improved functionality, improved power performance, improved yield, and an improved development environment.

Background

              Conventional flop designs fail if the set-up time requirement is exceeded, even if the timing violation is small.

              Some test products have features to change in-die clock delays. However, these features can only fix long-range systematic delay variations.

             

General description

              The disclosed method is a programmable delay flip flop (PDFF). The method simplifies the design flow and enables realignment of the flip-flop sampling edge during silicon debugging or high-volume production for unit recovery.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to tunable timing paths
•             Configurable power performance by reducing the operating voltage with a wider timing margin in the critical paths

•             Improved yield due to enabling unit recovery in silicon debug, including units with failures due to random short-range variations

•             Improved yield due to reducing yield loss from marginal set-up time violations

•             Improved productivity due to reducing the design throughput time

•             Improved development environment due to enabling the building of flop-based sequential circuits with a degree of tolerance to delay variation

•             Improved development cycle due to providing a test feature during silicon debug to pinpoint the failing stage along a data path so that more accurate design changes can be implemented if required

Detailed description

              The disclosed method is a PDFF network. The method simplifies design flow by synthesizing the PDFF using design automation tools. For example, predicting speed paths accurately in the design flow can be difficult. The PDFF can move the sampling edge of sequential circuits at locations where a marginal maximum delay failure occurs to the point where the path passes. In cases where source and receiver flip-flops along a data path have programmable delay elements, the front end of a data path can be tuned so the subsequent stages can ‘time borrow’ from the front-end stages.

              The disclosed method is a basis for the development of test features to optimally tune the delay settings of the PDFF network. The test features can lead to a realtime self-diagnosis capability that recovered a failing part during operation.

              In some designs, all flip flops cannot be in the PDFF network due to the large number of flops and the large bit-size requirement on the programmable read-only memory (PROM). In this case, designers can specify critical paths where the inclusion of the PDFF network is most beneficial. The choice of insertion stages follows an automated flow so that minimum designer intervent...