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Method for dual computations in a single pipeline for SER protection

IP.com Disclosure Number: IPCOM000127441D
Publication Date: 2005-Aug-30
Document File: 3 page(s) / 37K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for dual computations in a single pipeline for soft error rate (SER) protection. Benefits include improved functionality and improved power performance.

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Method for dual computations in a single pipeline for SER protection

Disclosed is a method for dual computations in a single pipeline for soft error rate (SER) protection. Benefits include improved functionality and improved power performance.

Background

              Soft errors are caused by alpha and neutron particles hitting a digital device and flipping a bit. Parity and error correction code (ECC) detect and correct these errors. With silent data corruption (SDC), the error is not detected and bad data is used or saved to disk. Different structures in a device have different levels of susceptibility to particles. The SER of a device is the sum of the structure multiplied by the susceptibility.

              When soft errors occur, the items to check include the following (see Figure 1):

•             Disk raid

•             Memory ECC

•             Cache ECC

•             Network ECC

•             Register array ECC

•             Memory raid

•             Pipeline latches

•             Combinational logic

•             Retry mechanism

•             Pipeline mirroring

•             Lockstep

General description

              The disclosed method is dual computations in a single pipeline for SER protection. The method includes a retry mechanism and pipeline mirroring. The retry mechanism enables a detected error to be corrected. The machine attempts the calculation again. Because the chances of getting a soft error a second time are extremely remote, detected but uncorrectable errors (DUE) are virtually eliminated from the pipeline.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing SER protection

•             Improved functionality due to providing a retry mechanism

•             Improved functionality due to providing pipeline mirroring
•             Improved power performance due to doubling the pipeline and ALU

Detailed description

              The disclosed method includes a retry mechanism and pipeline mirroring. Pipeline mirroring uses two copies of the pipeline and arithmetic logical units (ALUs) to calculate the same instruction at the same time. If one has a DUE, the other is assumed to be good. If the two calculations do not agree, a DUE exists. However, SDC is virtually eliminated. With a retry mechanism, DUE is virtually eliminated. Other logical units in the device require additional protection.

              Doubling the pipeline doubles the area required for the pipeline and ALUs. Doubling also dramatically increases the power because the pipeline and ALU are substantial providers of the total device power. However, p...