Browse Prior Art Database

Routability Sensitive Power Grid Design For Nanometer Technologies

IP.com Disclosure Number: IPCOM000127443D
Publication Date: 2005-Aug-30

Publishing Venue

The IP.com Prior Art Database

Related People

Chetan Verma: AUTHOR [+2]

Abstract

The idea being disclosed talks about an innovative way of the power grid design for ultra deep submicron technologies thereby gaining in terms of both the IR drop and routability of the design. This kind of power grid design will be good for any technology. But, it will be specially helpful in reducing die size for ultra deep sub micron designs (c90, c65 and lower).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 30% of the total text.

Page 1 of 12

Routability Sensitive Power Grid Design For Nanometer Technologies

   Chetan Verma (R49199) Ajit Kumar (R63848) Freescale India Design Center

Noida

Abstract

The idea being disclosed talks about an innovative way of the power grid design for ultra deep submicron technologies thereby gaining in terms of both the IR drop and routability of the design. This kind of power grid design will be good for any technology. But, it will be specially helpful in reducing die size for ultra deep sub micron designs (c90, c65 and lower).

copyright Freescale, Inc, 2005 1 of 12

[This page contains 2 pictures or other non-text objects]

Page 2 of 12

Introduction

With the designs moving to ultra deep sub-micron, the interconnects are playing a lot more dominant role than previously. Add to that the fact that there is a need to get more and more functionality into the designs and also that these designs are supposed to be working at lot higher frequencies. More functionality means more connectivity (and therefore more metal usage) and higher frequency of the designs leads to signal integrity and other metal wire related phenomenons which have to be duly taken care of, for design closures. The fact is that the physical gate sizes are scaling down but the metal sizes are not going down proportionately. And thats where the problem is!!

Problem Definition

One of the biggest observations made on nanometer designs has been that the die size is no longer dependent on the packing density of the standard cells. The routability of the design is the "gating" factor which determines the die size.This can be straightaway inferenced from the designs done in 90nm (cmos90). The packing density allowed by the cmos90 process is around 400Kgates/mm^2, but while implementation, the design teams have found it hard to go beyond even 300Kgates/mm^2.

copyright Freescale, Inc, 2005 2 of 12

[This page contains 2 pictures or other non-text objects]

Page 3 of 12

The standard cell utilization of most of the designs done in cmos90 has been lesser than 55%. This implies that as we go further down from cmos90 to cmos65, we would have greater packing density but the designs would not be able to leaverage the improved packing density to the fullest to optimize the die area because of the routing closure issues.

Solution

The solution to the above problem lies in the ability to provide more routing resources to the design at no extra die size and without affecting anything else. But how ?? The idea being disclosed talks about one such way of tackling this problem..through "a routability sensitive power grid design". This involves using different percentage of lower level and higher level metals for power grid so as to provide extra metal resources for signal routing of the design, without degrading the IR drop for the chip.

copyright Freescale, Inc, 2005 3 of 12

[This page contains 2 pictures or other non-text objects]

Page 4 of 12

Metal3


0.14


0.28


24


Metal4


0.14


0.28


24


Metal5


0.14


0.28


24...