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Aspect Ratio Driven Floorplan For IR Drop And Die Size Reduction

IP.com Disclosure Number: IPCOM000127444D
Publication Date: 2005-Aug-30

Publishing Venue

The IP.com Prior Art Database

Related People

Chetan Verma: AUTHOR [+3]

Abstract

A technique to improve the voltage drop and die size by correctly specifying the aspect ratio of a chip is being proposed. The idea, being disclosed, talks about the direction in which the aspect ratio of a chip should be chosen so as to improve the voltage drop and its distribution. If the metal flow directions and their resistivities and eventual aspect ratio are considered during floorplanning, the voltage drop and its distribution is improved and consequently, the die size can be reduced.

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Aspect Ratio Driven Floorplan For IR Drop And Die Size Reduction

   Chetan Verma (R49199) Anuj Singhania (R58657) Ajit Kumar (R63848) Freescale India Design Center

Noida

Abstract

A technique to improve the voltage drop and die size by correctly specifying the aspect ratio of a chip is being proposed. The idea, being disclosed, talks about the direction in which the aspect ratio of a chip should be chosen so as to improve the voltage drop and its distribution. If the metal flow directions and their resistivities and eventual aspect ratio are considered during floorplanning, the voltage drop and its distribution is improved and consequently, the die size can be reduced.

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Introduction

During the floorplanning of a chip, the intent always is to have a square chip with the aspect ratio of 1. With the design styles moving more towards the maximum IP reuse and SoC approach, more and more hard IPs and analog blocks are getting integrated on the same chip. Resultingly, more and more chips are becoming non-square (rectangular with aspect ratio slightly greater/lesser than 1. Everything then depends on the floorplanning to ensure that the voltage drop and die size are optimized. The guiding factors for the floorplanning are the io-pads placements, interblock connectivity, the module/hard-IP/memory sizes, modules to pads connectivity, routing congestion, power banking in the padrings and how best the modules can be put so as to minimize the die size.

We propose that for a non square chip, the aspect ratio of the chip MUST be modelled on the basis of the metal directions and resistivities. This implies that the higher level metal layer with lesser resistivity and its direction of flow should be used as a starting point for deciding which of x or y dimensions should be more.

A flow chart showing the comparsion between the older conventional process and the new one being proposed is shown below.

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Conventional Flow Proposed Flow

Board/Package

Constraints

Chip Pad Placements

Board/Package Constraints

Hard IP

Sizes

Interblock Connectivity

Hard IP

Sizes

Chip Pad Placements

Chip Aspect

Ratio

Block/Cell

Placements

Power Grid

Routing

Interblock Connectivity

Block/Cell

Placements

Power Grid

Routing

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Metal4

0.065

Horizontal

Metal5

0.065

Vertical

Metal6

0.022

Horizontal

Description:

The following example/table illustrates the point:

For a 6 metal layer cmos90 process

Table 1:

Metal

Sheet resistance (ohms/square)

Metal fLow direction

As can be seen, the sheet resistance of metal6 is approximately 3 times lesser than that of metal5. So, leaving aside other factors, theoretically, a single metal6 wire of a particular width/length will have 3...