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Novel Mask Logic for a Priority Encoder

IP.com Disclosure Number: IPCOM000127646D
Publication Date: 2005-Sep-07
Document File: 3 page(s) / 17K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an algorithm to create the necessary “head” and “tail” masks required to implement a priority encoder. Benefits include a reduction in design elements.

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Novel Mask Logic for a Priority Encoder

Disclosed is a method for an algorithm to create the necessary “head” and “tail” masks required to implement a priority encoder. Benefits include a reduction in design elements.

Background

Currently, priority determination in the Fast Store Forwarding Buffer (FSFB) is accomplished through the priority buffer and an age algorithm; however, this solution has design implications when a larger number of entries is used.

General Description

The disclosed method uses adder carry generation logic to simplify the design, and takes advantage of symmetries within the design. It reduces the relative area of the address buffer and priority logic in the current FSFB design by more than 65% and the total FSFB area by 35%. The disclosed method also expands the number of entries and address spaces with a 20% push in frequency, resulting in a performance gain. Furthermore,  the latency between the Store (STA) and load (LD) is reduced and has relaxed requirements on the STA and LD addresses. Generating the appropriate masks is a crucial requirement for enabling the disclosed method’s priority logic in FSFB (see Figure 1). The following formula is used to create the “head” and “tail” masks needed for the priority encoder:

For a 32 bit vector , the pointers have 5 bit sbid’s and n=4.  Using a group carry gen property of adders:

C4 = G(4) + P(4)G(3:2) + P(4)P(3:2)G(1:0)                                                                                            

The fourth bit is carried out only if it is generated from a group of (1:0) and propagated thru (3:2) and t...