Browse Prior Art Database

Charge Dumping for Improved Semiconductor Operation Performance

IP.com Disclosure Number: IPCOM000127662D
Original Publication Date: 2005-Oct-10
Included in the Prior Art Database: 2005-Oct-10
Document File: 3 page(s) / 237K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The speed of DRAM interfaces is constantly increasing. Nevertheless, the gap to microprocessor speed is constantly growing. Therefore, the DRAM is considered as a speed limiter in today’s computer systems. DRAM interfaces are currently operated on a clock speed of 400MHz (e.g. DDR-2 800). To a large extent this frequency is limited by off chip drivers (OCD). In a single DRAM a number of 32 OCD’s is switching simultaneously. The main reason for OCD noise is synchronous switching noise (SSN). SSN is caused by simultaneously switching OCD’s. If a great number of OCD’s is switching, the signal speed is reduced because of the great amount of noise. Therefore, data depending noise and signal performance will be generated. To reach considerably higher signal performance, new approaches must be made soon as highlighted in this disclosure. The principle of today’s OCD circuitry is schematically shown in fig. 1. The output stage basically consists of a big n-FET and p-FET which are individually controlled. They are connected to the I/O-pad with their drain connection and the source terminal is connected to VSSQ/VDDQ (supply voltage to the output buffers). Sometimes, buffer capacitors are provided in the vicinity of the OCD. Careful and symmetric design reduces power supply noise to some extent but it cannot solve the issue fundamentally. Even if on-chip-parasitics are reduced to a minimum (e.g. by extremely wide power busses) the connection from the chip to the external pad would remain highly inductive/resistive and it would increase the SSN at that. The right side of fig. 1 shows the inductive loops with involvement of local buffer capacitors (p/n-cap). The graph assumes signal state 1 to be driven at the output of the OCD. Local buffer p-cap is discharged by closing the switch S1. The discharging of p-cap will create a current loop through the I/O-pad and back trough VSSQ. However, since VDDQ is also connected, another current loop will occur through the I/O-pad and VDDQ. Because of the current and parasitics on VSSQ/VDDQ wires or on bond wire connections of the pads, a power drop occurs in both networks. The drop on VDDQ will cause other rising signals to be delayed while falling signals will be accelerated to negative VSSQ value. In case of a great amount of I/Os passing into signal state 1 and a small amount into state 0, strong SSN will be caused.

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Charge Dumping for Improved Semiconductor Operation Performance

Idea: Dr. Peter Poechmueller, DE-Munich

The speed of DRAM interfaces is constantly increasing. Nevertheless, the gap to microprocessor speed is constantly growing. Therefore, the DRAM is considered as a speed limiter in today's computer systems. DRAM interfaces are currently operated on a clock speed of 400MHz (e.g. DDR-2 800). To a large extent this frequency is limited by off chip drivers (OCD). In a single DRAM a number of 32 OCD's is switching simultaneously. The main reason for OCD noise is synchronous switching noise (SSN). SSN is caused by simultaneously switching OCD's. If a great number of OCD's is switching, the signal speed is reduced because of the great amount of noise. Therefore, data depending noise and signal performance will be generated. To reach considerably higher signal performance, new approaches must be made soon as highlighted in this disclosure.

The principle of today's OCD circuitry is schematically shown in fig. 1. The output stage basically consists of a big n-FET and p-FET which are individually controlled. They are connected to the I/O-pad with their drain connection and the source terminal is connected to VSSQ/VDDQ (supply voltage to the output buffers). Sometimes, buffer capacitors are provided in the vicinity of the OCD. Careful and symmetric design reduces power supply noise to some extent but it cannot solve the issue fundamentally. Even if on-chip-parasitics are reduced to a minimum (e.g. by extremely wide power busses) the connection from the chip to the external pad would remain highly inductive/resistive and it would increase the SSN at that. The right side of fig. 1 shows the inductive loops with involvement of local buffer capacitors (p/n-cap). The graph assumes signal state 1 to be driven at the output of the OCD. Local buffer p-cap is discharged by closing the switch S1. The discharging of p-cap will create a current loop through the I/O-pad and back trough VSSQ. However, since VDDQ is also connected, another current loop will occur through the I/O-pad and VDDQ. Because of the current and parasitics on VSSQ/VDDQ wires or on bond wire connections of the pads, a power drop occurs in both networks. The drop on VDDQ will cause other rising signals to be delayed while falling signals will be accele...