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Mid voltage range circuit topology improvement in zap trimming ESD protected circuit

IP.com Disclosure Number: IPCOM000127667D
Published in the IP.com Journal: Volume 5 Issue 9B (2005-10-10)
Included in the Prior Art Database: 2005-Oct-10
Document File: 3 page(s) / 72K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

An ESD (ElectroStatic Discharge) procedure (zap) on integrated circuits (IC) usually creates a short between parts of the IC. The zapping is accomplished in test phase before packaging. Proper functionality before and after zapping must be realized. Therefore a new circuitry is introduced that features further protection to guarantee the correct and expected functionality. The risk for the ESD structures to be shorted inadvertently is abolished. A previous solutions used in integrated circuits is shown in Fig.1. The proposed circuit is shown in Fig. 2. Both systems consist of: a) A zap-pad, used to apply high voltage for a short time to melt the zap-structure; b) A zap-structure that is normally an open circuit and, once melted, becomes a short circuit towards ground, bringing the voltage at that node to zero; c) A resistor R used as a current limiter for protection; d) A zener diode used for protection; e) A p-channel MOS (P1) with the source connected to Vsupply and the gate connected to ground, used to keep the drain at a high potential, if the zap-structure is not burnt; f) A p-channel MOS (P2) and an inverting gate used as positive feedback on the drain of P1 voltage; g) An output pin connected to a certain logic circuitry that senses the voltage and propagates this information to be used for modifying currents and voltages in bandgaps etc. When a technology with high voltage logic gates is used (Vsupply=7V), due to the low Vds of P1, the zap-structure can start wasting current and deteriorating all performances of the circuit. This is a very risky situation and a source of inaccurate functionality.

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Mid voltage range circuit topology improvement in zap trimming ESD protected circuit

Idea: Prof. Alberto Gola, IT-Padova; Salvatore Piccolella, IT-Padova; Alberto Flore, IT-Padova;

Nicola Macri, IT-Padova

An ESD (ElectroStatic Discharge) procedure (zap) on integrated circuits (IC) usually creates a short between parts of the IC. The zapping is accomplished in test phase before packaging. Proper functionality before and after zapping must be realized. Therefore a new circuitry is introduced that features further protection to guarantee the correct and expected functionality. The risk for the ESD structures to be shorted inadvertently is abolished.

A previous solutions used in integrated circuits is shown in Fig.1. The proposed circuit is shown in Fig.
2. Both systems consist of:
a) A zap-pad, used to apply high voltage for a short time to melt the zap-structure;
b) A zap-structure that is normally an open circuit and, once melted, becomes a short circuit towards ground, bringing the voltage at that node to zero;
c) A resistor R used as a current limiter for protection;
d) A zener diode used for protection;
e) A p-channel MOS (P1) with the source connected to Vsupply and the gate connected to ground, used to keep the drain at a high potential, if the zap-structure is not burnt;
f) A p-channel MOS (P2) and an inverting gate used as positive feedback on the drain of P1 voltage;
g) An output pin connected to a certain logic circuitry that senses the voltage and propagates this information to be used for modifying currents and voltages in bandgaps etc.

When a technology with high voltage logic gates is used (Vsupply...