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Method for an automated power-grid integrity check

IP.com Disclosure Number: IPCOM000127679D
Publication Date: 2005-Sep-08
Document File: 2 page(s) / 38K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an automated power-grid integrity check. Benefits include improved functionality, improved performance, and improved reliability.

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Method for an automated power-grid integrity check

Disclosed is a method for an automated power-grid integrity check. Benefits include improved functionality, improved performance, and improved reliability.

Background

              Computer aided design (CAD) tools are conventionally used to create a system-on-a-chip (SOC) design for generating power grids. This process typically works successfully for small designs. However, for complex SOC designs, the process has a high chance of failure due to tool capacity limitations. Typical problems include failing to drop vias and failing to drop an optimal number of vias.

              The result is power reliability concerns. The silicon does not function as expected due to failure in power distribution throughout the chip. The conventional solution is a painstaking visual inspection of all intersections to ensure the correctness of the power grid.

Description

              The disclosed method is an automated search of all power grid intersections, a check for the correct presence of vias, and counts for the optimum number of vias.

              The disclosed method performs the following steps (see Figure 1):
1.           Tool extracts selective metal design layers and text associated with the power grid.

2.           Metal polygons with text are marked as a power grid.

3.           Power grids are checked for the correct width and failures are reported. This step repeats until all errors are detected and fixed.

4.           Tool searches for all overlapping a...