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A Technique to Improve Performance of MPEG/H264 Video Decoder For Low Motion Video Applications using Vector Processor.

IP.com Disclosure Number: IPCOM000127739D
Original Publication Date: 2005-Sep-12
Included in the Prior Art Database: 2005-Sep-12
Document File: 6 page(s) / 52K

Publishing Venue

Motorola

Related People

Vijaya Yagnanarayana: AUTHOR [+3]

Abstract

Motion Compensation for video decoding in standards like MPEG and H.264 typically take more than 50% of the computational time, a new technique is proposed to speed up this process for low motion video sequence. This technique can be primarily employed for systems which have vector processors as video decode accelerators. The typical gain using this technique on an ideal vector processor can be more than 50% for a low motion video sequence. An ideal vector processor satisfies the below equation.

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A Technique to Improve Performance of MPEG/H264 Video Decoder For Low Motion Video Applications using Vector Processor.

Vijaya Yagnanarayana, Mike Schuette and Raghavan Subramaniyan

Abstract:

Motion Compensation for video decoding in standards like MPEG and H.264 typically take more than 50% of the computational time, a new technique is proposed to speed up this process for low motion video sequence. This technique can be primarily employed for systems which have vector processors as video decode accelerators. The typical gain using this technique on an ideal vector processor can be more than 50% for a low motion video sequence. An ideal vector processor satisfies the below equation.

 ---------- Eqn(1)

for

Where is the time required to doiterations. In most video processing systems, accommodating the largeindirectly translates to operating on large vectors chunks.

Practical vector processors are not ideal; Performance on these processors is dictated by two factors: startup overhead and loop execution time. The startup overhead is fixed and the loop execution time varies according to the vector length. The proposed technique reduces the repeated calls to vector processor there by saving the start-up time and increasing the number of iterations done per call there by significant savings in loop-execution time. Practical Vector processors employ various optimization techniques to reduce the loop execution time and thus the gain that can be achieved using the proposed technique is variable based on the hardware architecture and tools.

Introduction:

Vector processors are primarily designed to solve large scientific and engineering problems. The data for these complex problems exhibit the kind of parallelism that these processors will exploit to process them in a single/few cycle/s, the similar computation would require a loop to do in a scalar processor. The advancements in the semiconductor technology and the new areas of computation like video processing have resulted in the resurgence of these processors in embedded multimedia markets. Typical multimedia processing on the embedded systems involves significant computations. The media data organization and most of the computationally significant algorithms in the media processing chain can be represented as vector stream (media data) and data flow graphs (algorithm) that operate on these vector streams [1]. The key challenge in optimizing the performance on these systems is to vectorize the data need for algorithm and making sure the size of the vectors on which  algorithm is operated is large enough to obtain the significant gain.[ Refer Eqn (1) above].

Technique:

Basic Motion Compensation algorithms in MPEG4 and H.264 is block based compensation of 16X16 size macro-blocks. Encoder has option to do various mode decisions, to choose smaller blocks/partition to represent motion more finely, but for large regions of same or no motion, encoder need to limit the motion compensation block size to 16...