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A Finite Impulse Response Filter for Controlling Channel Echo in High Speed Chip-to-Chip Interconnects

IP.com Disclosure Number: IPCOM000127759D
Publication Date: 2005-Sep-13
Document File: 2 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a conventional two-tap transmit finite impulse response filter (FIR) with a long delay stage to eliminate the need for doubly-terminating the transmission line of a chip-to-chip interconnect. Benefits include increased net power savings.

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A Finite Impulse Response Filter for Controlling Channel Echo in High Speed Chip-to-Chip Interconnects

Disclosed is a method that uses a conventional two-tap transmit finite impulse response filter (FIR) with a long delay stage to eliminate the need for doubly-terminating the transmission line of a chip-to-chip interconnect. Benefits include increased net power savings.

Background

High speed chip-to-chip interconnects require the double termination of transmission lines to minimize signal reflections and their resulting data errors. These terminations consume a significant amount of the total I/O circuit power.

The state of the art for high speed chip-to-chip interconnects is to sacrifice power by terminating the transmission line at both ends of the link. It is impractical to reduce power by increasing impedances, because of the resulting negative impacts on crosstalk, electromagnetic interference, and PCB thickness.

General Description

Figures 1 through 4 show the disclosed method with various interconnect termination and signal integrity conditions for a low frequency data pattern. The driver current for the doubly-terminated scheme is shown in Figure 1 with a one volt transmit, signal amplitude, a matched 50 ohm transmission system, and a center-tapped load termination of 10 mA. The power for the schemes of Figure 2 and 3 averages half that, or 5 mA, with random data. The signal integrity in Figure 3 is corrupted by the presence of a connector or other impedance disconti...