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Method for a DDR strobe weak pull-down resistor for correct strobe capture

IP.com Disclosure Number: IPCOM000127760D
Publication Date: 2005-Sep-13
Document File: 2 page(s) / 46K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a double data rate (DDR) strobe weak pull-down resistor for correct strobe capture. Benefits include improved functionality, improved reliability, and improved cost effectiveness.

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Method for a DDR strobe weak pull-down resistor for correct strobe capture

Disclosed is a method for a double data rate (DDR) strobe weak pull-down resistor for correct strobe capture. Benefits include improved functionality, improved reliability, and improved cost effectiveness.

Background

              Conventionally, DDR synchronous dynamic random access memory (SDRAM) memory systems use a bidirectional strobe (DQS pin) to assist the controller/memory to synchronize data. The strobe is driven by the DDR SDRAM when reading the memory. The strobe is driven by the DDR controller when writing to memory. When reading from DDR memory, the controller must enable its input receivers at the correct time. If enabled before the SDRAM starts to drive the strobe, the controller may detect a tristate value on the strobe and latch incorrect data. If the controller input receivers are enabled after the SDRAM starts to drive the strobe, the first beats of a DDR burst may be missed.

              Conventionally, controllers must enable their input receivers during the small window of time described in “DDR2 SDRAM Specification”, published by JEDEC as document #JESD-79-2B on January, 2005. During a read, DDR SDRAM is driving both the strobe (DQS pin) and the data (DQ pin). The preamble is the time defined as tRPRE. The controller must enable during this window. If the controller enables early, it receives a tristated DQS and possibly latches incorrect data. If the controller enables late, it can miss the first rising edge of the strobe and miss the first beat of the data burst (see Figure 1).

              Enabling the input receivers during thetRPRE window is difficult for the controller because the DQS and DQ signals coming from the DDR memory are asynchronous (unknown phase) to the controller’s internal clock. The delay through the pads, the board trace delay, and the tAC access time of the DDR SDRAM is not known by the controller and changes with process, voltage, and temperature....