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Method for a hybrid CML/CMOS quarter-rate clocking with nibble deskew on DRAM

IP.com Disclosure Number: IPCOM000127764D
Publication Date: 2005-Sep-13
Document File: 5 page(s) / 265K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a hybrid current mode logic/complementary metal oxide semiconductor (CML/CMOS) quarter-rate clocking with nibble deskew on dynamic random-access memory (DRAM). Benefits include improved functionality, improved performance, and improved power performance.

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Method for a hybrid CML/CMOS quarter-rate clocking with nibble deskew on DRAM

Disclosed is a method for a hybrid current mode logic/complementary metal oxide semiconductor (CML/CMOS) quarter-rate clocking with nibble deskew on dynamic random-access memory (DRAM). Benefits include improved functionality, improved performance, and improved power performance.

Background

              Clock distribution and phase generation are required for high-speed data links using DRAM. Conventionally, clock signals are distributed through all-CMOS clock trees without deskew on DRAM.

              In DRAM technologies, conventional CMOS clock trees drive the high-speed DRAM I/O. These clock trees are often comprised of multiple branches and/or multiple phases, where branches or phases are designed to match one another in propagation delay. Distributing a clock signal through a CMOS clock tree with power supply and thermal noise can cause jitter, which can be amplified through the clock tree due to bandwidth limitation. Mismatches in transistors and interconnects contribute to skew among branches and phases. A clock tree with branches spanning thousands of microns is more likely to have significant skew because of systematic process variation. Furthermore, as the data transfer rate in DRAM I/O increases beyond 4.8 GT/s and the 1-µi width shrinks below 208 ps, jitter and skew comprise a larger percentage of the timing.

General description

              The disclosed method addresses the problem of clocking a high-speed DRAM-to-memory-controller and DRAM-to-DRAM data link. The method includes hybrid CML/CMOS quarter-rate clocking, source-synchronous clocking with low-jitter CML clocking, and low-power CMOS clocking, which is an original approach to reaching a jitter and power trade-off.

      A deskewing scheme, called nibble deskew, enables each group of adjacent input/output (I/O) cells (nibble) to independently trim clock edges against data eyes, improving setup/hold margin and link robustness. Nibble deskew reduces the power consumption of global clock distribution circuitry.

              The quarter-rate clock distribution circuitry is comprised of the following:

•             CML buffers

•             CMOS inverters

•             Voltage-controlled delay lines

•             Phase interpolators

•             CML-to-CMOS converters

•             Interconnects

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to balancing jitter and power in clocking high-speed data links by employing a combination of CML and CMOS clocking
•             Improved performance due to reducing bit-by-bit skew by trimming active clock edges against data eyes within the nibble with dual-phase interpolators providing 0º and 90º clock phases

•             Improved power performance due to using voltage-controlled delay lines in each nibble with voltage-controlled delay lines in each nibble

Detailed description

      The discl...