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Method for all CML ¼-rate clocking with nibble deskew on DRAM I/O

IP.com Disclosure Number: IPCOM000127765D
Publication Date: 2005-Sep-13
Document File: 4 page(s) / 201K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for all current mode logic (CML) ¼-rate clocking with nibble deskew on dynamic random access memory (DRAM) input/output (I/O). Benefits include improved functionality, improved performance, and improved power performance.

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Method for all CML ¼-rate clocking with nibble deskew on DRAM I/O

Disclosed is a method for all current mode logic (CML) ¼-rate clocking with nibble deskew on dynamic random access memory (DRAM) input/output (I/O). Benefits include improved functionality, improved performance, and improved power performance.

Background

              As microprocessors increase in computing speed, the memory interface speed becomes a bottleneck for platform performance. The conventional memory I/O circuit topology of matched data and clocking paths is no longer adequate due to the required data rate increases and power, jitter, and process limitations. Clock distribution and phase generation are required for high-speed data links using DRAM.

      Conventionally, clock signals are distributed through all-complementary metal oxide semiconductor (CMOS) clock trees without deskew on DRAM. High-speed memory uses the matched clocking and data path for source-synchronous clocking architecture. As the required memory interface data rate increases, the matched clock and data path with CMOS buffers do not function successfully due to the exponentially increased power with the limited DRAM process. The clock skew caused by transistor mismatch and interconnect-routing mismatch require tight link timing (see Figure 1).

              A nibble is comprised of four adjacent I/O cells.

              Compared to the conventional ¼-rate CMOS clock tree, all CML clocking reduces clock jitter by 90% and power increases by 225%.

General description

              The disclosed method includes unmatched ¼-rate CML clocking to improve the clock jitter using an acceptable amount of power. The method provides nibble deskew by using local voltage-controlled delay line and phase interpolators (PI) to trim the sampling clock edges at the optimal position with respect to the data eye in the link-training sequence. One nibble shares a delay line and PI to balance the clock distribution power and timing. The local clock distribution within the nibble is matched as closely as possible.

              The disclosed method is a clocking method for high-speed memory I/O. The method enables a data rate up to 4.8 Gb/s with low-speed DRAM processes. A data receiver that is compatible with CML clock inputs results in improved setup/hold and voltage sensitivity performance.

              The key elements of the disclosed method include:

•             ¼-Rate clock distribution tree with CML buffers to dramatically reduce the clock j...