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Enhancing the accuracy of LRU replacement mechanism for the secondary and tertiary (and all next) levels of cache

IP.com Disclosure Number: IPCOM000127768D
Original Publication Date: 2005-Sep-13
Included in the Prior Art Database: 2005-Sep-13
Document File: 1 page(s) / 20K

Publishing Venue

IBM

Abstract

Propagation of usage information from a primary to secondary cache for non-inclusive topology's.

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Enhancing the accuracy of LRU replacement mechanism for the secondary and tertiary (and all next) levels of cache

Consider an on-chip cache hierarchy that includes a primary cache (often referred to as an L1 cache) and a secondary cache (often referred to as an L2 cache). The invention may also prove useful for other levels of caching (say L2 and L3).

A normal scenario involves loading a cache line from memory into the primary and secondary caches. The cache line may remain resident for a long time in the primary cache without the secondary cache being made aware of the usage in the primary cache. Thus, the line may be replaced in the secondary cache (if the primary and secondary caches are non-inclusive). This results in less effective caching.

The invention propagates usage information from the primary cache to the secondary cache on a regular basis. Thus, the history (or LRU information) for cache lines in the secondary cache reflects usage in the primary cache.

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