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MOSSIM II:. A Switch-Level Simulator for MOS LSl User's Manual

IP.com Disclosure Number: IPCOM000127922D
Original Publication Date: 1982-Dec-31
Included in the Prior Art Database: 2005-Sep-14
Document File: 34 page(s) / 93K

Publishing Venue

Software Patent Institute

Related People

Randy Bryant: AUTHOR [+5]

Abstract

MOSSIM II is a logic simulator based on the switch-level logic model described in the Phd thesis of R. Bryant [2]. It models a MOS digital circuit as a network of nodes connected by transistor "switches" and hence can accurately model such circuit structures as (bidirectional) pass transistors, ratioed and complementary logic, busses, dynamic memory, and charge sharing. Unlike analog circuit simulators, MOSSIM utilizes a logical model and hence operates at speeds comparable to conventional logic gate simulators. Very large designs can be simulated for long input sequences with reasonable computational cost. This program supersedes an earlier version of MOSSIM [1]. It has superior performance, a more general network model, and more powerful simulation capabilities. MOSSIM II is written in Mainsail (TM)* and hence can run on a variety of computer systems.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

CALIFORNIA INSTITUTE OF TECHNOLOGY Computer Science

MOSSIM II:. A Switch-Level Simulator for MOS LSl User's Manual

by

Randy Bryant Mike Schuster Doug Whiting This work was funded in part by Defense Advanced Research Contracts Agency ARPA Order Number 3771 and by the Caltech Silicon Structures Project Copyright California Institute of Technology, 1982

MOSSIM II: A SWITCH-LEVEL SIMULATOR FOR MOS LSI USER'S MANUAL 25 January 1983

Randy Bryant Mike Schuster Doug Whiting

Table of Contents 2. 3. 4. 5. Introduction Network Model Simulation Timing Models The X State Simulator Commands 5.5. 5.1. Vectors 5.2. Constants 5.3. Commands 5.4. System Set Up
5.4.1. READ 5.4.2. WRITE 5.4.3. CLOCK 5.4.4. WATCH 5.4.5. UNWATCH Symbol 5.5.1. VECTOR 5.5.2. CONSTANT 5.5.3. PREFIX 5.5.4. UNPREFIX Run Control 5.6.1. INITIALIZE
5.6.2. DUMP 5.6.3. LOAD 5.6.4. UPDATE 5.6.5. CYCLE 5.6.6. PHASE 5 . fi . 7 . STEP 5.7. Node Manipulation 5.7.1. GET 5.7.2. VERIFY 5.7.3. STATUS 5.7.4. SET 5.7.5. FORCE 5.7.6. UNFORCE 5.7.7. CHARGE 5.8. Breakpoint Manipulation 5.8.1. BREAK 5.8.2. UNBREAK 5.9. Operational Control 5.9.1. SOURCE 5.9.2. EXECUTE 5.9.3. COPY 5.9.4. COMMENT 5.9.5. SWITCH 5.9.6. LIMIT 5.9.7. HELP 5.9.8. QUIT 5.9.9. EXIT 6. Network Description Language
6.1. Nodes 5.6. Table Manipulation

1 2 5 7 8 9 9 9 11 11 11 11 12 12 12 12 13 13 14 14 14 1~4 15 15 15 16 16 16 16 17 17 18 18 19 19 19 19 20 20 20 20 20 21 21 22 23 23 23 24 24

6.2. Node Primitives 26 6.3. Transistor Primitives 27 6.4. Net Definitions 27 6.5. Block Calls 28
6.6. Subnetwork Inclusion 28 7. The CONVERT Program 29 7.1. Commands 30 7.1.1. EXTRACT 30 7.1.2. NETWORK 30 7.1.3. STRENGTH 30 7.1.4. SIZE 31 7.1.5. TYPE 32 7.1.6. NODE 32 7.1.7. INSERT 32 7.1.8. DELETE 33 7.1.9. STATUS 33 7.1.10. PARAMETER 33
7.1.11. WRITE 33 7.1.12. HELP 34 7.1.13. QUIT 34 7.1.14. EXIT 34 8. The MOSCHK Program 34 8.1. Commands 35 8.1.1. READ 35 8.1.2. TECHNOLOGY 36 8.1.3. CHECK 36 8.1.4. HELP 36 8.1.5. QUIT 36 8.1.6. EXIT 36 9. Simulation Example 37 I. The NTK Network Description Format 41 II. Functional Block Interface 44 III. Simulator Driver Interface 48 IV. Installation 49

List of Figures

Figure 2-1: Switch-Level Model of Three Transistor Dynamic RAM Cell 2 Figure 2-2: Switch- Level Models of Logic Gates 4 Figure 3-1: Simulation Phases for a Two-Phase, Nonoverlapping Clock 5 Figure 9-1: Quasi-Static Register with Multiplexor on Output 37 Figure 9-2: NDL program for the Network of Figure 9-1 37 Figure II-1: Procedural Implementation of a Quasi- Static Register 45 Figure II-2: NDL Shift Register program using the functional block 45 Figure III-1: Driver Procedure to Build Truth Table 48

1. Introduction

California Institute of Technology Page 1 Dec 31, 1982

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MOSSIM II:. A Switch-Level Simulator for MOS LSl User's Manual

MOSSIM II is a logic simulator based on the switch-level logic model described in the Phd thesis of R. Bryant [2]. It models a M...