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SUBMICRON SYSTEMS ARCHITECTURE

IP.com Disclosure Number: IPCOM000127926D
Original Publication Date: 1982-Dec-31
Included in the Prior Art Database: 2005-Sep-14

Publishing Venue

Software Patent Institute

Related People

Lennart Johnsson: AUTHOR [+4]

Abstract

This document reports the research activities and results for the period October 1 1981 - October 15 1982 under the Defense Advanced Research Project Agency (ARPA) Submicron Systems Architecture Project. The central theme of this research is the architecture and design of VLSI systems appropriate to a microcircuit technology scaled to submicron feature sizes, and includes related efforts in concurrent computation and design tools. Much of the work at Caltech on advanced design tools and designer workstations is supported separately within the industry- and NSF-sponsored Silicon Structures Project (SSP), and is reported elsewhere. Where there is some overlap in support between ARPA and SSP, or where a graduate student may be supported by a fellowship, this additional support is indicated in reporting that effort.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 3% of the total text.

Page 1 of 49

THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

SUBMICRON SYSTEMS ARCHITECTURE

28 October 1982

.

SEMIANNUAL TECHNICAL REPORT

Edited and in part written by

Lennart Johnsson and Charles L. Seitz

Co-principal investigators: Charles L. Seitz, Carver A. Mead, Lennart Johnsson

Other faculty: Randal Bryant, Jim Kajiya, Alain Martin, Martin Rem

Staff: Jim Campell, Vivian Davies, Pete Hunter, Michael Newton

Ph.D. students: Young-il Choo, Erik DeBenedictis, Peggy Li, Sheue-Ling Lien, Mike Ullner, Dan Whelan, Doug Whiting

M.S. students: Bill Athas, Chao-Lin Chiang, Howard Derby, Eric Holstege, Chris Lutz, Charles Ng, John Ngai, Craig Steele

Undergradute students: Steve Rabin, Don Speck

Computer Science

CALIFORNIA INSTITUTE of TECHNOLOGY

1. Overview

1.1 Scope of this Report

This document reports the research activities and results for the period October 1 1981 - October 15 1982 under the Defense Advanced Research Project Agency (ARPA) Submicron Systems Architecture Project.

The central theme of this research is the architecture and design of VLSI systems appropriate to a microcircuit technology scaled to submicron feature sizes, and includes related efforts in concurrent computation and design tools.

Much of the work at Caltech on advanced design tools and designer workstations is supported separately within the industry- and NSF-sponsored Silicon Structures Project (SSP), and is reported elsewhere. Where there is some overlap in support between ARPA and SSP, or where

California Institute of Technology Page 1 Dec 31, 1982

Page 2 of 49

SUBMICRON SYSTEMS ARCHITECTURE

a graduate student may be supported by a fellowship, this additional support is indicated in reporting that effort.

1.2 Scope of the Research

The submicron systems architecture project is a carefully integrated research effort, in which theory is closely tied to experiments in VLSI architecture and design. The various aspects of the research tend to support each other. To the extent that they can be separated, the several research areas can be listed as follows:

- Architectures that can exploit the capabilities of VLSI technology.

- Concurrent algorithms for important and demanding computations.

- Theory of Concurrent computation applied to the representation of algorithms and switching systems.

- Design disciplines that manage the complexity of VLSI systems.

- Design tools that check and enforce these disciplines.

Let us try to explain the close connection and common motivation of these areas.

What is driving this research effort are the opportunities and problems presented by VLSI technology. As microcircuit technology is scaled to features at submicron dimensions, it presents an opportunity of a dramatic reduction in cost/performance, represented by the cube- law scaling of the switching energy Esw, and of an increase in the complexity of chips. However, there are attendant problems in learning how to exploit this opportunity.

Where communication is recognized e...