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Delayering and Fibbing Free Analog Macro for Failure Analysis

IP.com Disclosure Number: IPCOM000127927D
Original Publication Date: 2005-Sep-14
Included in the Prior Art Database: 2005-Sep-14
Document File: 6 page(s) / 83K

Publishing Venue

IBM

Abstract

Putting a subset circuits of analog macro in the Kerf and bringing up all the circuit nodes in the subsets to the chip surface by wirings and vias will make delaying and fibbing free FA analog macros. The probing pads will be contacted one at a time, and it will be done for FA characterization purpose, which allows us to make it very small, 2--5um squre.

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Delayering and Fibbing Free Analog Macro for Failure Analysis

1. Background

ASIC chips have a few analog macros most of the time. Some chips have many analog macros. Analog measurements are taken on such chips at the wafer final test and the module final test and checked for the distribution. Its mean and sigma vary lot to lot. Some lots have bad yields, compared to others. And it is not easy to find the root cause of the variation.

Early this year, we had DAC test high fallout. A majority of the fails were due to marginal voltage measurement(Vref) fails. We took such failed chips for FA(failure analysis) to find out what portion of circuits were defective. However, FA was not an easy task. We wanted to measure voltage of each node of the Vref circuits, but delayering and fibbing of the circuits rendered the FA difficult to perform FA. It was impossible to measure all the physical nodes for many devices.

2. Prior Art

2-1. There are no analog macros in the Kerf, which are the same(or subset) as the analog macros in a chip. Therefore the FA needs to be done using the chip itself, where there are many wiring on top of the analog macros and it makes it difficult to perform FA.

2-2. FA of functional circuits is a very challenging task for failure analysis on current CMOS technologies due to the need to contact various metal levels simultaneously without damaging the circuit. Current methodology is to use a Focused Ion beam (FIB) tool to selectively cut contacts to the desired level, and then back fill with tungsten thereby creating a FIB test point which then can be contacted on a probe station. It is not unusual for many such test points to be needed for any given circuit and the location of these contacts can be greatly complicated by underlying features which cannot be damaged by the FIB operation. While the FIB can also deposit an insulator layer which allows the operator to place the test points anywhere convenient, the time required to 'wire up' one of these circuits can be a major factor. Also, the analyst is always concerned about the quality of the FIB contacts, and whether they are making good ohmic contact to the desired mask level. Another question is whether 'over spray' from the FIB deposition of the tungsten is allowing leakage between test points. Finally, after all this preparation time has been spent, it is always possible to damage the 'fine' FIB lines on the probe station, requiring repair to be performed in the FIB tool. Such repairs, however, raise questions about whether the repair

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corrected the problem and whether extended time in charged ION beam of the tool affected the circuit performance, etc.

The following schematic(Fig. 1) illustrates one such test point deposition from LM to M2. This is typical and was used extensively on characterization of a DAC circuit on CMOS7SF Vulcan product.

Fig. 1

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Fig.2

This optical micrograph illu...