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A Comparison of MOS PLAs

IP.com Disclosure Number: IPCOM000127928D
Original Publication Date: 1982-Dec-31
Included in the Prior Art Database: 2005-Sep-14
Document File: 4 page(s) / 19K

Publishing Venue

Software Patent Institute

Related People

Stephen Trimberger: AUTHOR [+3]

Abstract

There is no universal agreement about the relative merits and long-term advantages of nMOS, CMOS-SOS and CMOS-Bulk technologies. Fundamental limitations on line widths and power loading strongly affect the final geometry size. However, the geometrical design rule spacings and electrical rules may prevent a promising technology from reaching its full potential. This paper discusses PIA designs in three MOS technologies: nMOS, CMOS/SOS and CMOS-Bulk The purpose of this paper is not to introduce a new and exciting PLA design, nor is it to recommend one fabrication technol-ogy over another. Its purpose is to use PLAs as a standard, hopefully familiar layout strategy so that new designers can get a better understanding of the advantages and disadvantages of all three technologies from a designer's viewpoint. It is hoped that this paper will provide more data to those who must select a technology for their integrated circuit fabrication.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

A Comparison of MOS PLAs

Stephen Trimberger California Institute of Technology Pasadena California 91125

5059: TM: 82

0 California Institute of Technology

A Comparision to MOS PLAs

There is no universal agreement about the relative merits and long-term advantages of nMOS, CMOS-SOS and CMOS-Bulk technologies. Fundamental limitations on line widths and power loading strongly affect the final geometry size. However, the geometrical design rule spacings and electrical rules may prevent a promising technology from reaching its full potential.

This paper discusses PIA designs in three MOS technologies: nMOS, CMOS/SOS and CMOS- Bulk The purpose of this paper is not to introduce a new and exciting PLA design, nor is it to recommend one fabrication technol-ogy over another. Its purpose is to use PLAs as a standard, hopefully familiar layout strategy so that new designers can get a better understanding of the advantages and disadvantages of all three technologies from a designer's viewpoint. It is hoped that this paper will provide more data to those who must select a technology for their integrated circuit fabrication,

The nMOS PLA

The PLA shown in figure 1 is an nMOS implementation of the traffic light con-troller from [Mead 1980]. The PLA has three inputs, ten minterms, five out-puts and two feedback terms. The inputs and outputs connect at the bottom. The AND-plane is on the left and the OR-plane is on the right. All the PU examples in this paper are arranged like this.

Both the AND-plane and the OR-plane in the nMOS PLA are composed of NOR gates, so the input drivers invert the input signals and the output drivers invert the results to give an OR of ANDs output.

The CMOS-Bulk PLA

A precharged dynamic CMOS Bulk PLA is shown in figure 2. This PLA is based on a design by
C. Seitz [Seitz 1982]. The PLA AND-plane is composed of NAND gates which are precharged high, Between the planes is a precharged inverter, and the outputs are inverted, yielding a NAND-NOT-NOR-NOT sequence, which gives the OR of ANDs.

The PLA programming for the PLA in figure 2 is the same as the program-ming for the NMOS PLA. Although the array cells are appro3dmately the same size, the drivers for the CMOS

California Institute of Technology Page 1 Dec 31, 1982

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A Comparison of MOS PLAs

design are much larger and the CVMOS design has an inverter and precharge circuitry between the planes.

There are four causes of the greater size. First, MMOS Bulk has geometrical design rules which require large spacing at well boundries [Griswold 1982]. Leaving the P-well requires an 8 lambda metal between pieces of diffusion. When contacts and contact to transistor spacing are added, the minimum distance between pullup and pulldown is 18 lambda, compared to 4 lambda for NMOS. Of course, the CMOS pullup, is a minimum length transistor, so about 6 lambda is saved. The result is a 8 lambda difference for each inver...