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CONCURRENT FAULT SIMULATION OF MOS DIGITAL CIRCUITS

IP.com Disclosure Number: IPCOM000127929D
Original Publication Date: 1983-Dec-31
Included in the Prior Art Database: 2005-Sep-14
Document File: 12 page(s) / 45K

Publishing Venue

Software Patent Institute

Related People

Michael D. Schuster: AUTHOR [+4]

Abstract

The concurrent fault simulation technique is widely used to analyse the behavior of digital circuits in the presence of fauns. We show how this technique can be applied to metal-oxide-semiconductor (MOS) digital circuits when modeled at the switch-level as a set of charge storage nodes connected by bidirectional transistor switches. The algorithm we present is capable of analysing the behavior of a wide variety of MOS circuit failures, such as stuck at-$ero or stuck-at-one nodes, stuck open or stuck-closed transistors, or resistive opens or shorts. We have implemented a fault simulator FMOSSIM based on this algorithm. The capabilities and the performance of this program demonstrate the advantages of combining switch-level and concurrent simulation techniques. This research was supported in part by the IBM Corporation and by the Defense Advanced Research Contracts Agency, ARPA Order 3771. Michael Schuster was supported in part by a Bell Laboratories Ph.D. Scholarship. Artech House, 1984 , CONCURRENT FAULT SIMULATION OF MOS DIGITAL CIRCUITS Michael D. Schuster and Randal E. Bryant Department of Computer Science California Institute of Technology Pasadena, California 91125

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

CONCURRENT FAULT SIMULATION OF MOS DIGITAL CIRCUITS

Michael D. Schuster and Randal E. Bryant

California Institute of Technology Pasadena, California 91125

5101:TM:83 To be presented at the Conference on Advanced Research is VLSI, to be held at the Massachusetts Institute of Technology, January 1984. Proceedings published by Artech Horse, Inc., Dedham, MA 02028.

ABSTRACT

The concurrent fault simulation technique is widely used to analyse the behavior of digital circuits in the presence of fauns. We show how this technique can be applied to metal-oxide- semiconductor (MOS) digital circuits when modeled at the switch-level as a set of charge storage nodes connected by bidirectional transistor switches. The algorithm we present is capable of analysing the behavior of a wide variety of MOS circuit failures, such as stuck at-$ero or stuck-at-one nodes, stuck open or stuck-closed transistors, or resistive opens or shorts. We have implemented a fault simulator FMOSSIM based on this algorithm. The capabilities and the performance of this program demonstrate the advantages of combining switch-level and concurrent simulation techniques.

This research was supported in part by the IBM Corporation and by the Defense Advanced Research Contracts Agency, ARPA Order 3771. Michael Schuster was supported in part by a Bell Laboratories Ph.D. Scholarship.

Artech House, 1984 , CONCURRENT FAULT SIMULATION OF MOS DIGITAL CIRCUITS Michael D. Schuster and Randal E. Bryant Department of Computer Science California Institute of Technology Pasadena, California 91125

ABSTRACT

The concurrent fault simulation technique is widely used to analyze the behavior of digital cir- cuits in the presence of faults. We show how this technique can be applied to metal oxide- semicon-ductor (MOS) digital circuits when modeled at the switch-level as a set of charge storage nodes con-nected by bidirectional transistor switches. The algorithm we present is capable of analysing the behavior of a wide variety of MOS circuit failures, such as stuck-at-zero or stuck-at-one nodes, stuck open or stuck-closed transistors, or resistive opens or shorts. We have implemented a fault simulator FMOSSIM based on this algorithm. The capabili-ties and the performance of this program demon-strate the advantages of combining switch level and concurrent simulation techniques.

INTR ODUTCTION

California Institute of Technology Page 1 Dec 31, 1983

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CONCURRENT FAULT SIMULATION OF MOS DIGITAL CIRCUITS

Test engineers use fault simulators to deter-mine how well a sequence of test patterns, when applied to the inputs of an integrated circuit, can distinguish a good chip from a defective one. The fault simulator is given a description of the good circuit, a set of hypothetical faults in the circuit, a specification of the observation points of the test (e.g. the output pins of the chip, and a se-quence of test patterns. It then sim...