Browse Prior Art Database

SUBMICRON SYSTEMS ARCHITECTURE

IP.com Disclosure Number: IPCOM000127933D
Original Publication Date: 1983-Dec-31
Included in the Prior Art Database: 2005-Sep-14
Document File: 23 page(s) / 69K

Publishing Venue

Software Patent Institute

Related People

Office of Naval Research: AUTHOR [+3]

Abstract

bytes of primary storage, and the total node complexity of 4 MSL allows nodes per chip. A prototype mosaic tree with mosaic processors connected to 8K bytes of off-chip RAM will be operating later this spring, shortly after the next batch of mosaic chips arrives from MOSIS. The logistics of possibly building a useful size prototype of this system are closely tied to mosaic-mesh. As previously reported, even with this small amount of storage and the tree interconnection, a 1000 chip mosiac-tree would be capable of performing an interesting variety of numerical and graph computations with very high performance.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

SUBMICRON SYSTEMS ARCHITECTURE

Semiannual Technical Report

California Institute of Technology

5078:TR:83

April 1983 Sponsored by Defense Advanced Research Projects Agency ARPA Order Number 3771

Monitored by the Office of Naval Research Contract Number N00014-79-C-0597 bytes of primary storage, and the total node complexity of 4 MSL allows nodes per chip. A prototype mosaic tree with mosaic processors connected to 8K bytes of off-chip RAM will be operating later this spring, shortly after the next batch of mosaic chips arrives from MOSIS. The logistics of possibly building a useful size prototype of this system are closely tied to mosaic-mesh. As previously reported, even with this small amount of storage and the tree interconnection, a 1000 chip mosiac-tree would be capable of performing an interesting variety of numerical and graph computations with very high performance.

(4) Super-mesh is an SIMD machine in the early stages of design. Its elements are expected to be quite small, about 1 MSL, containing only registers, serial floating point arithmetic, and neighbor communication. An instruction cycle of this machine requires several more clock cycles than its mantissa word length, and a microcode control word is transmitted serially for each instruction cycle. The physical design of this machine employs a deliberate skew in the internode communication and instruction broadcast to allow it to be extended to any size, but its interconnection is limited to a mesh. This machine might be regarded as a very efficient implementation of a computational or systolic array, with the advantage that the system is programmable for a variety of applications. A study of applications has revealed a number of limitations in this model that suggests that a useful machine will have to have either a large amount of storage per node or a very high bandwidth access mechanism to a secondary storage system.

2.2 Cosmic Cube

2.2.1 Hardware

William C Athas, Pete Hunter, Chuck Seitz

Design and prototyping efforts for this project were reported in our previous semiannual technical report. Hardwire efforts for the Cosmic Cube have centered in the past 6 months on logistics for assembling and testing the 6-cube (64 processor) machine.

PC boards for the processors were delivered in February, and almost all of the integrated circuit and packaging parts have been delivered in the January to March period. The processor boards have been populated with sockets and components at the rate of two boards per day, and are

California Institute of Technology Page 1 Dec 31, 1983

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SUBMICRON SYSTEMS ARCHITECTURE

now almost all assembled. These boards are being tested in a test fixture consisting of a cosmic cube Intermediate Host (IH) and a degenerate cube.

The intermediate host has been redesigned and simplified to a standard 86/12A multibus system with a single wire-wrapped Cube Life Support (CLS) b...