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DESIGN of the MOSAIC ELEMENT

IP.com Disclosure Number: IPCOM000127937D
Original Publication Date: 1983-Dec-31
Included in the Prior Art Database: 2005-Sep-14
Document File: 10 page(s) / 36K

Publishing Venue

Software Patent Institute

Related People

Chris Lutz: AUTHOR [+6]

Abstract

The Mosaic element is a fast single chip com-puter designed to be used in groups for concurrent computation experiments. Each element contains a 15-bit processor, read-write storage, read-only store for a small initialization and bootstrap loading pro-gram, four input ports, and four output ports. The Mosaic processor, a highly structured design that achieves -very good performance and density through innovations in its microcode, circuit techniques, and layout, is described in detail.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

DESIGN of the MOSAIC ELEMENT

Chris Lutz Steve Rabin Chuck Seitz Don Speck

5093:TR: 83

Computer Science Cali.fornia Institute of Technology Pasadena CA 91125

The research described in this paper was sponsored by The Defense Advanced Research Projects Agency ARPA order number 3771 and monitored by the Office of Naval Research under contract number N00014-79-C-0597

ABSTRACT

The Mosaic element is a fast single chip com-puter designed to be used in groups for concurrent computation experiments. Each element contains a 15-bit processor, read-write storage, read-only store for a small initialization and bootstrap loading pro-gram, four input ports, and four output ports. The Mosaic processor, a highly structured design that achieves - very good performance and density through innovations in its microcode, circuit techniques, and layout, is described in detail.

INTRODUCTION

Myriads of Mosaic elements can be connected together by their ports in a variety communication plans to form a family of specialized, high perfor-mance, concurrent, and programmable computing engines. In addition to its end use as a component for experiments with concurrent computing engines, the Mosaic element has been an interesting vehicle for numerous adventures in VLSI design, design tools, and testing. It includes experiments and innovations in its microcode, circuit techniques, and layout, with performance being a central objective throughout.

A Mosaic element with 4K bytes of read-write storage, approximately 140K transistors on a chip 4000 lambda square (6 mm square at 3 micron fea-ture size), is sufficiently complex to have given our design tools a thorough workout, and have stretched our capabilities for laying out, verifying, and testing large structured designs.

The original models for this project were (1) Sally Browning's research on algorithm for a programmable tree machine123 and (2) the `Om" de-scribed in Mead & Couway4. Mosaic started out as a tree machine element, but we have since come to see it as a building block for a variety of fine grain en-semble machines3 -with connection plans up to degree four, such as a tree, mesh, shuffle, chordal ring, or cube connected cycle. The influence of the OM2 on. the processor datapath layout is apparent.

Several early attempts to lay out a much less ambitious processor with a.4-bit path to off-chip stor-age managed to break our design tools, and were thus indirectly the origin of the constraint solving composition and geometry tool Earls used for the present design- A new processor with a 16-bit path to storage that could be placed on-chip was designed in 1982, sent to MOSIS in

California Institute of Technology Page 1 Dec 31, 1983

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DESIGN of the MOSAIC ELEMENT

January 1983, and functioned essentially correctly, and at 7 MHz (4 micron feature size), on first silicon in February 1983. The processor design was subsequently augmented to...