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Hot-Clock nMOS

IP.com Disclosure Number: IPCOM000127941D
Original Publication Date: 1985-Dec-31
Included in the Prior Art Database: 2005-Sep-14
Document File: 9 page(s) / 36K

Publishing Venue

Software Patent Institute

Related People

Charles L Seitz: AUTHOR [+8]

Abstract

Each time the signal x is to change 0 --+ 1, the power supply must provide a quantity of charge CYdd at potential Vdd, hence energy CYdd2. Half of this energy ends up stored in the capacitance C, and the other half is dissipated in the p-channel transistor. When x is to change 1 -* 0, the charge stored on C is conducted through the n-channel transistor into the ground terminal, and the stored energy is dissipated in the transistor. Thus in a full cycle 0 --* 1 --* 0 of signal x, energy CYdds must be supplied to the chip, and is dissipated in. the transistors that drive this signal. The fundamental motivation behind hot-clock nMOS is to get around this "inevitable" dissipation of power on a high-complexity chip.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

Hot-Clock nMOS

Charles L Seitz Alexander H Frey Sven Mattisson Steve D Rabin Don A Speck Jan L A van de Snepscheut

Computer Science Department California Institute of Technology

5177:TR:85

The research described in this paper was sponsored by Defense Advanced Research Projects Agency, ARPA Order No. 3771, and monitored by the Office of Naval Research under contract number N0001 4-79-C-0597

California Institute of Technology, 1984

to appear in Proceedings, 1985 Chapel Hill Conference on VLS Each time the signal x is to change 0 --+ 1, the power supply must provide a quantity of charge CYdd at potential Vdd, hence energy CYdd2. Half of this energy ends up stored in the capacitance C, and the other half is dissipated in the p-channel transistor. When x is to change 1 -* 0, the charge stored on C is conducted through the n-channel transistor into the ground terminal, and the stored energy is dissipated in the transistor. Thus in a full cycle 0 --* 1 --* 0 of signal x, energy CYdds must be supplied to the chip, and is dissipated in. the transistors that drive this signal. The fundamental motivation behind hot-clock nMOS is to get around this "inevitable" dissipation of power on a high-complexity chip.

If one were to try to spot the places on a MOS chip where most of the dynamic power goes, it would be in the drivers of relatively large capacitances - long and/or highly loaded wires - that are driven at relatively high frequencies. Examples of such signals are control lines and data buses in instruction and arithmetic processors; word and bit lines in RAMS; literal and implicant lines in large PLAs, and output pads. By virtue of their capacitance, these are also signals that are difficult to drive with small delay.

Many of these signals are naturally driven in synchrony with one of the clock signals, so another possibility is to drive them through some approximation to an ideal switch:

(Image Omitted: Figure 2)

Here we assume that the output is initially 0, and that the enable signal changes only during 02 in a two-phase non-overlapping clocking scheme. The output is then 01 Aertable. If the switch were ideal, the circuit would introduce no delay, the output being just a gated replica of the input clock. Also, the switch turns on only when there is no voltage across it, and off when there is no current flowing through it, so even if it did exhibit some non-zero resistance or conductance while switching, it dissipates no power in changing state. Assume that when this switch is implemented with MOS transistors, it can be modeled as an ideal switch in series with an effective resistance

R, and that the clock transition can be modeled as a ramp from OV to Y. in time t" and from Y., to OV in time t f:

California Institute of Technology Page 1 Dec 31, 1985

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Hot-Clock nMOS

(Image Omitted: Figure 3)

Let the switch be on. If t, were 0, the full clock voltage would appear...