Browse Prior Art Database

SUBMICRON SYSTEMS ARCHITECTURE

IP.com Disclosure Number: IPCOM000127954D
Original Publication Date: 1986-Dec-31
Included in the Prior Art Database: 2005-Sep-14

Publishing Venue

Software Patent Institute

Related People

Charles I. Seitz: AUTHOR [+3]

Abstract

The central theme of this research is the architecture and design of VLSI sys-tems appropriate to a microcircuit technology scaled to submicron feature sizes. Our work is focused on VLSI architecture experiments that involve the design, construc-tion, programming, and use of experimental message-passing concurrent computers, and includes related efforts in concurrent computation and VLSI design. - Additional background information can be found in previous semiannual tech- nical reports (5052:TR:82], (5078:TR:83], (5103:TR:831, (5122:TR:841, (5160:TR:841, [5178:TR:85], [5202:TR:85], (5220:TR:861.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

SUBMICRON SYSTEMS ARCHITECTURE

Semiannual Technical Report

Department of Computer Science California .institute of Technology

5235:TR:86 5 December 1986 Reporting Period: 16 March 1986 to 15 November 1986

Principal Investigator: Charles I. Seitz

Faculty Investigators: James T Kajiya Alain J Martin Robert J McEliece Martin Rem Charles L Seitz Sponsored by the Defense Advanced Research Projects Agency ARPA Order Number 3771

Monitored by the Office of Naval Research Contract Number N00014-79 SUBMICRON SYSTEMS ARCHITECTURE - Department of Computer Science _* California Institute of Technology

1. Overview and Summary

1.1 Scope of this Report

This document is a summary of the research activities and results for the eight month period, 16 March 1986 to 15 November 1986, under the Defense Advanced Research Project Agency (DARPA) Submicron Systems Architecture Project. Tech-nical reports covering parts of the project in detail are listed following. these sum-maries, and can be ordered from the Caltech Computer Science Library.

1.2 Objectives

The central theme of this research is the architecture and design of VLSI sys-tems appropriate to a microcircuit technology scaled to submicron feature sizes. Our work is focused on VLSI architecture experiments that involve the design, construc-tion, programming, and use of experimental message-passing concurrent computers, and includes related efforts in concurrent computation and VLSI design.

- Additional background information can be found in previous semiannual tech- nical reports (5052:TR:82], (5078:TR:83], (5103:TR:831, (5122:TR:841, (5160:TR:841, [5178:TR:85], [5202:TR:85], (5220:TR:861.

1.3 Highlights

Some highlights of the previous 8 months are:

California Institute of Technology Page 1 Dec 31, 1986

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SUBMICRON SYSTEMS ARCHITECTURE

* All sections of the Mosaic C designed and laid out (sections 2.2.3 and 4.1).

* Cantor programming language operational and in use (sections 2.2.2 and 3.1). * Joint projects initiated with two companies to build prototype second generation "cubes" (section 2.3) . * New results in compiling multiprocess programs to self-timed VLSI designs (sec-tion 4.2). -1-

2.1 Cosmic Cube Project

W C Athas, Michael Lichter, Wen-King Su, Chuck Seitz The Cosmic Cubes and Intel iPSC continue to run very reliably, with researchers at Caltech and at other DARPA sites using them for application programming projects. Usage has been moderately heavy. Our own most intensive use has been for event-driven simulations of designs for the second generation message-passing multicomputers (see sections 2.3 and 3.4) . A system supporting Cantor, a fine grain concurrent object-oriented program-ming language, is now available and in regular use on the Cosmic Cubes and iPSC (see section 3.1).

2.1.1 Hardware and System Software Status

Neither the 64-node nor 8-node Cosmic Cubes has exhibited a hard failure in this 8-month per...