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THE LOGICAL STRUCTURE OF THE MEMORY RESOURCE IN THE SYMBOL 2R COMPUTER

IP.com Disclosure Number: IPCOM000127986D
Original Publication Date: 1973-Dec-31
Included in the Prior Art Database: 2005-Sep-14
Document File: 12 page(s) / 43K

Publishing Venue

Software Patent Institute

Related People

Hamilton Richards, Jr.: AUTHOR [+4]

Abstract

As has been reported elsewherel-5, the SYMBOL-2R computer system's basic design premises included the following:

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

THE LOGICAL STRUCTURE OF THE MEMORY RESOURCE IN THE SYMBOL 2R COMPUTER

Hamilton Richards, Jr.

Roy J. Zingg

October 1973

This paper was presented at the Symposium on the High-Level Language Computer Architecture University of Maryland, College Park, Maryland November 1973

1. INTRODUCTION

As has been reported elsewherel-5, the SYMBOL-2R computer system's basic design premises included the following:

1. implementation of a user-oriented high-level programming language directly in hardware; 2. provision of int eractive computing ser-vice for as many as 31 independent user terminals simultaneously; 3. incorporation of a virtual-memory system, using a small core memory to buffer a large paging drum. In this paper, we shall touch only peripherally on the last two of these premises; aur chief concern here is to describe those aspects of SYMBOL's mem- ory structure that impinge upon the first premise, namely, direct high-level language implementation.

The SYMBOL system is composed of several sub-stantially independent processors, each of which contributes a unique function to the operation of the system. The processors most intimately involved in the implementation of the SYMBOL programming language6 are the Translator (TR)7,8, which trans-lates the source program supplied by the user into an internal object program, and the Central Proces-sor (CP)9, which then executes the object program. Also involved are the Input/output Processor (IP)10* and the Channel Controller (CC), which pro-vide communications between the user and his pro-gram. The activities of the various processors are coordinated by a processor known as the System Supervisor. The arrangement of these user-oriented processors is depicted in Fig. 1. As this figure shows, the user-oriented processors do not interact directly with core memory, but instead address their requests for memory services to yet another processor, the Memory Controller (MC). The struc-ture of the memory resource provided by the Memory Controller will be our chief topic in this paper.

2. STORAGE AT SEVERAL LEVELS

In a typical conventional system, the FORTRAN programmer has one view of memory, the assembly-language programmer another, and the designer of

The Input/Output processor was referred to in certain early literature as the "Interface Processor".

Iowa State University Page 1 Dec 31, 1973

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THE LOGICAL STRUCTURE OF THE MEMORY RESOURCE IN THE SYMBOL 2R COMPUTER

(Image Omitted: Fig. 1. SYMBOL - 2R system block diagram.)

the CPU still another. In a similar vein, it is possible to describe SYMBOL-2R's storage facili-ties on several different levels. For the pur-poses of this paper, we shall discern a hierarchy containing four such levels, namely, user-level storage, logical storage, virtual storage, and physical storage. We shall devote the remainder of this section to a brief description of each of these levels in terms of the o...