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A low power video compression chip for portable applications

IP.com Disclosure Number: IPCOM000128126D
Original Publication Date: 1999-Dec-31
Included in the Prior Art Database: 2005-Sep-15
Document File: 7 page(s) / 22K

Publishing Venue

Software Patent Institute

Related People

Simon, Thomas D: AUTHOR [+3]

Related Documents

http://theses.mit.edu:80/Dienst/UI/2.0/Describe/0018.mit.theses/1999-154: URL

Abstract

This thesis describes the development of a low power, single chip video encoder intended for battery operated portable applications. Such an encoder is intended to serve as part of the DSP in a portable device which might image, data convert, compress, and transmit video signals. The encoder described in this thesis is designed with the goal of minimizing system power, minimizing utilized bandwidth, and maximizing system integration. The encoder achieves a peak power dissipation of several hundred uW while scalably compressing a video stream of 8 bit gray scale, 30 frame/sec, and 128x128 demonstration resolution. The encoder scales up for greater resolutions at mostly linear cost. The compression is performed using wavelet filtering and a combination of zero-tree and arithmetic coding of filter coefficients, all integrated on a single demonstration chip. The compression results achieved (a tradeoff curve of compression factor versus PSNR) are on par with the best available based on wavelet filters. The above results do not include the use of motion compensation, however, hooks are implemented at the algorithmic and architectural levels to add motion compensation at the cost of power dissipation a few times higher. These results are obtained by the careful coordination of design in a deep vertical manner, ranging from system, algorithmic, and architectural to circuit, floor planning, and layout. This thesis describes the motivation of the design goals, the interlinking vertical design choices, and the results achieved.

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 This record is the front matter from a document that appears on a server at MIT and is used through permission from MIT. See http://theses.mit.edu:80/Dienst/UI/2.0/Describe/0018.mit.theses/1999-154 for copyright details and for the full document in image form.

A Low Power Video Compression Chip for Portable Applications

by

Thomas Simon
Bachelor of Science in Electrical Engineering Massachusetts Institute of Technology, June 990 Master of Science in Electrical Engineering and Computer Science Massachusetts Institute of Technology, September 1994
Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science

at the Massachusetts Institute of Technology

June 1999
SIGNATURE OF author: [[signature omitted]]

Department of Electrical Engineering and Computer Science

April 30, 1999
CERTIFIED BY: [[SIGNATURE OMITTED]]

Anantha Chandrakasan, Ph.D.

Associate Professor of Electrical Engineering Thesis Supervisor ACCEPTED BY: [[SIGNATURE OMITTED]]

Arthur Clarke Smith, Ph.D.

Professor of Electrical Engineering Graduate Officer ARCHIVES MASSACHUSETTS INSTITUTE OF TECHNOLOGY LIBRARIES JUL 15 1999

Massachusetts Institute of Technology Page 1 Dec 31, 1999

Page 2 of 7

A low power video compression chip for portable applications

[2]

A Low Power Video Compression Chip for Portable Applications

by

Thomas Simon

Submitted to the Department of Electrical Engineering and Computer Science on April 30, 1999 in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science

Abstract

This thesis describes the development of a low power, single chip video encoder intended for battery operated portable applications. Such an encoder is intended to serve as part of the DSP in a portable device which might image, data convert, compress, and transmit video signals. The encoder described in this thesis is designed with the goal of minimizing system power, minimizing utilized bandwidth, and maximizing system integration. The encoder achieves a peak power dissipation of several hundred uW while scalably compressing a video stream of 8 bit gray scale, 30 frame/sec, and 128x128 demonstration resolution. The encoder scales up for greater resolutions at mostly linear cost. The compression is performed using wavelet filtering and a combination of zero-tree and arithmetic coding of filter coefficients, all integrated on a single demonstration chip. The compression results achieved (a tradeoff curve of compression factor versus PSNR) are on par with the best available based on wavelet filters. The above results do not include the use of motion compensation, however, hooks are implemented at the algorithmic and architectural levels to add motion compensation at the cost of power dissipation a few times higher. These results are obtained by the careful coordination of design in a deep vertical manner, ranging from system, algorithmic, and arch...