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ENGINEERING DESIGN REPORT: PDP-7/MODIFIED 338 DISPLAY INTERFACE

IP.com Disclosure Number: IPCOM000128414D
Original Publication Date: 1967-Aug-01
Included in the Prior Art Database: 2005-Sep-15
Document File: 5 page(s) / 22K

Publishing Venue

Software Patent Institute

Related People

Lundstrom, Stephen F.: AUTHOR [+3]

Abstract

The purpose of the interface to the PDP-7 described below is to allow the modified DEC 338 display control (a DEC 338 display without a PDP-8 processor) to operate with the PDP-7 as its processor. The resulting interface will accept any device that will interface to a PDP-8 except those using the extended data-break facility (three-cycle data break). The addition of such a feature would be a logical extension of the design of this interface but was not attempted because no need existed for it at the time of the original design, and thus it was not economically attractive

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

ENGINEERING DESIGN REPORT: PDP-7/MODIFIED 338 DISPLAY INTERFACE

The purpose of the interface to the PDP-7 described below is to allow the modified DEC 338 display control (a DEC 338 display without a PDP-8 processor) to operate with the PDP-7 as its processor. The resulting interface will accept any device that will interface to a PDP-8 except those using the extended data-break facility (three-cycle data break). The addition of such a feature would be a logical extension of the design of this interface but was not attempted because no need existed for it at the time of the original design, and thus it was not economically attractive

This report will serve as a progress report for those interested in technical progress on the project, and as a maintenance manual for those responsible for system maintenance in the future. Basic design objectives and decisions will be described first A brief discussion of programming objectives will be followed by a detailed description of the logic involved. An appendix includes a comparison of corresponding interface logic signals on the PDP-8 and the PDP-7.

The only major design decision was to decide what part of the 18-bit PDP-7 word to use to provide the 12-bit PDP-8 data. It was decided to have the data bits associated with the PDP-8 data be the low-order 12 bits. This decision allows the programmer of the modified 338 display to use the high-order bits of core as special flag bits so that the 338 display program may be imbedded in a larger data structure. It also allows use of the LAW (Load Address Word) instruction of the PDP-7 to set up initialization of the display with the programmed accumulator transfer instructions with a minimum of storage requirements. Arguments concerning the instruction field being high-order bits and the sign-bit being the high order bit were not considered to be overriding because of the different order codes of the two computers and because the PDP-7 generally uses diminished-radix-complement (one's complement) arithmetic while the PDP-8 uses radix complement (two's complement) arithmetic. Thus representations of negative numbers are different in the two machines. High-order sign-bits are not advantageous as far as the display is concerned, since no data formats have the high-order bit set for negative moves. Logic is provided in the interface to gate the PDP-7 device address (bits 6-11) into the corresponding PDP-8 device address location when not in a data-break cycle. Figure 1 shows the correspondence of accumulator data bits, and Figure 2 shows the correspondence of memory buffer data bits.

PROGRAMMING CONSIDERATIONS

The same device addresses and input-output pulse (IOP) numbers that the 338 system uses are effective in the PDP-7/modified 338 display system except for the locations of the bits in the PDP-7 instructions. PDP-7 subdevice addresses are not used, but the clear-accumulator bit remain...