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Design Analysis Tool for Generating Memory Models for Disparate Design Methodologies and Method Thereof

IP.com Disclosure Number: IPCOM000128429D
Publication Date: 2005-Sep-15
Document File: 5 page(s) / 107K

Publishing Venue

The IP.com Prior Art Database

Related People

Jayanta Bhadra: AUTHOR [+3]

Abstract

In modern high performance microprocessors, embedded memories account for approximately half the area and more than 50% of the transistors. Because of their ubiquitous nature modeling memories remains an immensely important part of the design methodology. Adding to the challenge of memory modeling is a complication that arises from the requirement that the memories need to be modeled for each individual debug methodology-testing, formal verification, validation, emulation, and so on. We describe a tool (MemGen) that automates generation of all memory models required by testing, verification, and emulation methodologies.

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Design Analysis Tool for Generating Memory Models for Disparate Design Methodologies and Method Thereof

Jayanta Bhadra, Magdy S. Abadir, and Ekaterina Trofimova

Freescale Semiconductor Inc.

Abstract

In modern high performance microprocessors, embedded memories account for approximately half the area and more than 50% of the transistors. Because of their ubiquitous nature modeling memories remains an immensely important part of the design methodology. Adding to the challenge of memory modeling is a complication that arises from the requirement that the memories need to be modeled for each individual debug methodology – testing, formal verification, validation, emulation, and so on. We describe a tool (MemGen) that automates generation of all memory models required by testing, verification, and emulation methodologies.

Motivation

The area of this paper is automated of memory model generation. Stand-alone high performance microprocessors as well as Systems-on-Chips (SoCs) [5, 4, 11, 14, 15, 10, 13] typically have a large number of embedded memories. These include general purpose registers, caches, tags, look-up tables, branch history tables, and other memories unique to the architecture. Embedded memories need to be modeled carefully to support various verification, test, and emulation methodologies that are involved in the overall design methodology. In the existing methodology, given a high level specification of a memory individual models of the memory are manually generated. The correctness of each model has also to be checked. Often writing test benches and proving correctness is manual, error-prone and tedious. Multiple iterations might be required before the models are finally obtained. Another aspect is mutual consistency. All the models are inter-related because each has to match the implementation of the final chip. Also, if the test model is not equivalent with the verilog model and tests generated using the verilog model fail on the silicon, one might end up shipping bad chips as good and rejecting good chips as bad. The new invention that we present results into a tool called MemGen, that automatically generates all the memory models from the same high level memory specification. It thus guarantees that all the models generated are mutually equivalent and correct by construction. We also have an extra step to prove correctness using a formal technique to be explained later.

The new methodology is illustrated in the following figure. The tool MemGen is used to automate generation of all memory models required by the design, test, simulation, emulation methodologies.

Model generation and validation

For system-level validation and block-level formal verification the RTL model of each embedded memory contains (a) custom RTL random logic and (b) MemGen-generated RTL model for each instantiated memCore resembling the above RAM model. At the block level, formal verification ensures that the RTL model is bugfree. At the system level, RTL...