Browse Prior Art Database

ANALYSIS OF MULTIPLE- BUS INTERCONNECTION NETWORKS

IP.com Disclosure Number: IPCOM000128473D
Original Publication Date: 1984-Feb-01
Included in the Prior Art Database: 2005-Sep-16
Document File: 7 page(s) / 97K

Publishing Venue

Software Patent Institute

Related People

T. N Mudge: AUTHOR [+6]

Abstract

A new analytic performance model is presented for multiprocessor systems employing multiple bus interconnection networks. The system bandwidth is analyzed as a two stage process taking into account conflicts arising from memory and bus interference. The analysis covers multiple bus systems in which each memory is connected to every bus, and systems in which each memory is connected to a subset of the buses. The model is compared to previously published simulation data and is shown to be in close agreement.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 15% of the total text.

Page 1 of 7

THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

ANALYSIS OF MULTIPLE- BUS INTERCONNECTION NETWORKS

T. N. Mudge, J. P. Hayes, G.D. Buzzard and D. C. Winsor

CRL-TR-12-84

THE UNIVERSITY OF MICHIGAN COMPUTING RESEARCH LABORATORY1

FEBRUARY 1984

Room 1079, East Engineering Building

Ann Arbor, Michigan 481011
USA
Tel: (313) 763-8000

ANALYSIS OF MULTIPLE BUS INTERCONNECTION NETWORKS2by
T. N. Mudge, J. P. Hares, G. D. Buzzard and D. C. Winsor

University of Michigan
Computing Research Laboratory
Room 1079 East Engineering Bldg.

Ann Arbor, MI 48109 USA

Abstract

A new analytic performance model is presented for multiprocessor systems employing multiple bus interconnection networks. The system bandwidth is analyzed as a two stage process taking into account conflicts arising from memory and bus interference. The analysis covers multiple bus systems in which each memory is connected to every bus, and systems in which each memory is connected to a subset of the buses. The model is compared to previously published simulation data and is shown to be in close agreement.

I. Introduction

A great deal of attention has been paid to the design and analysis of interconnection networks for multiprocessor systems. Most of the previous research has dealt with crossbar networks or multistage networks 3. While these networks are attractive for applications where high bandwidth is required, their high cost and special implementation requirements hare prevented them from being used for the full range of multiprocessor applications. Most commercial systems containing more than one processor employ a single bus; consider, for example, the design philosophy advocated for the iAPX86 family in which the Multibus (IEEE 796 standard

1 This work was supported by the National Science Foundation, under the Grants No. ECS-8214709 and MCS- 8009315.

2 This work was supported by the National Science Foundation, under the Grants No. ECS-8214709 and MCS8009315.

3 Computer, vol. l4, no. l2, Dec. 1981.

University of Michigan Computing Research Laboratory Page 1 Feb 01, 1984

Page 2 of 7

ANALYSIS OF MULTIPLE- BUS INTERCONNECTION NETWORKS

bus) provides all the intrasystem communication 4. Single bus systems are inexpensive and easy to implement but have limited bandwidth and lack fault tolerance. A natural extension is to employ several shared buses to increase bandwidth and fault tolerance at moderate cost. Figure 1 shows typical systems in which B buses are used to interconnect N processors to M memory modules (B ≤ N). Unlike a crossbar or multistage network, a multiple bus interconnection scheme allows easy incremental expansion of the number of processors and memories in the system. Furthermore, the buses can be configured in a variety of ways to provide a range of trade-offs between bandwidth, connection cost, and reliability.

Recently, Lang, et al. 5,6 have investigated multiple bus systems of the kind depicted in Figure 1. Using simulation they determined t...