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Directions in High Performance Computation

IP.com Disclosure Number: IPCOM000128724D
Original Publication Date: 1987-Dec-31
Included in the Prior Art Database: 2005-Sep-16
Document File: 13 page(s) / 47K

Publishing Venue

Software Patent Institute

Related People

S. Lennart Johnsson: AUTHOR [+3]

Abstract

The evolving technology is driving high performance computer architecture towards highly concurrent systems. We review some of the elements of the technology influenc-ing this direction, and discuss some of the architectural, algorithn-.dc, and programming system consequences of this change. Finally, we briefly describe some of the essential fea-tures of the Connection Machine, a commercially available computer with an architecture and programming system that includes several of the features we expect to find in many high performance architectures in the future.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

Directions in High Performance Computation

S. Lennart Johnsson Department of Computer Science Yale University New Haven, CT 06520

June 1987

*Presented at Computer Science and Statistics. 19th Symposium on the Interface

Abstract

The evolving technology is driving high performance computer architecture towards highly concurrent systems. We review some of the elements of the technology influenc-ing this direction, and discuss some of the architectural, algorithn-.dc, and programming system consequences of this change. Finally, we briefly describe some of the essential fea-tures of the Connection Machine, a commercially available computer with an architecture and programming system that includes several of the features we expect to find in many high performance architectures in the future.

1 Introduction

There are several technological facts that drives the design of high performance computers in the direction.of highly concurrent systems. High performance systems have traditionally been built of the fastest technology available, such as bipolar technology. Such architec-tures are expensive, and consume a large amount of power. The price has exceeded that of a standard mainframe by at least an order of magnitude, and the peak performance been at least two orders of magnitude higher than that of a mainframe. The performance measured over complete application codes typically falls in the range 10% - 30% of the peak performance.

There are several reasons for this large descrepancy between peak and average perfor-mance. For many years processors in high performance architectures has been faster than the storage units. Fast processors have storage that is interleaved. To balance the stor-age bandwidth with that of a processor between 8 and 64 storage banks per processor are common. Including a cache in the architecture reduces the need for primary storage band-width, if the algorithms exhibit locality. Register oriented architectures have significantly lower bandwidth to storage than to registers. Hence, if the operations have operands that resides in primary storage then the performance is often significantly less than peak performance. With operands in storage, the situation may be further aggravated if suc-cessive requests for storage operations are directed to the same storage unit. In this case the performance is determined by the bank bandwidth, not the full storage bandwidth. A stride that equals a multiple of the number of banks is particularly unfortunate. In cache based architectures a small stride, preferably one, with respect to the machine data

'Currently on leave at Thinking Machines Corp. structure. (linear ordering) is important to reduce the number of cache misses. Bank con-flicts and cache misses may reduce the performance by an order of magnitude. All current high performance architectures have pipeli~ed functional units (and are known as vector architectur...