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Provide platform specific run time services using the hypervisor system calls for PowerPC processor in native SMP mode

IP.com Disclosure Number: IPCOM000128814D
Original Publication Date: 2005-Sep-19
Included in the Prior Art Database: 2005-Sep-19
Document File: 1 page(s) / 26K

Publishing Venue

IBM

Abstract

Disclosed is an utilization of the PowerPC (*) hypervisor call instruction and the Hypervisor Interrupt Offset Register (HIOR) to provide platform service functions when the system is in non-partitioned native mode.

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Provide platform specific run time services using the hypervisor system calls for PowerPC processor in native SMP mode

During Initial Power Load (IPL), the system firmware puts aside the memory space for the platform service module so that operating system (OS) does not see this reserved memory. The system firmware loads the platform service module into this reserved memory, and fix the module so that it operates properly at this runtime base address. The system firmware instructs PowerPC 970 processors to set the HIOR to the base address of the reserved memory space before handling control over to the OS.

At the beginning of the platform service module (offset 0) is the array of the

context-saving buffer address initialized by the system firmware when the module is loaded and relocated into the HIOR address.

At the hypervisor call vector (offset 0xC00) of the module, the interrupt handler will

save General Purpose Register (GPR) 1 into Special Purpose Register (SPRG) 2 which is used as a scratch pad register for context-saving code.

The handler retrieves the context-saving buffer address into GPR1. The handler then

saves the relevant GPRs and Condition Register (CR) into the context buffer. Retrieve the sc instruction based on which executing-context (SRR0/SRR1) it came


4.

from. Then Identify it to be normal system call instruction sc(0) or hypervisor call instruction sc(1).

For sc(0) call, restore the register context, then execute absolute branch to address

0x...