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An Analysis of a Mesa Instruction Set

IP.com Disclosure Number: IPCOM000128916D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Sep-20

Publishing Venue

Software Patent Institute

Related People

McDaniel, G.: AUTHOR [+3]

Abstract

This paper discusses Mesa's byte encoding, patterns of memory references, use of an expression evaluation stack, and the costs of emulating 32-bit operations on a 1 6-bit processor.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

©; Xerox Palo Alto Research Center, June 1982

An Analysis of a Mesa Instruction Set

Gene McDaniel

CSL-82-2 May 1982 [ PB20003l ]
(I) Association for Computing Machinery 1982. Printed with permission.

Abstract: This paper reports measurements of dynamic instruction frequencies for two Mesa programs running on a Dorado personal computer at the Computer Science Laboratory of the Xerox Palo Alto Research Centers. The patterns of use associated with the Mesa instruction set are examined in order to find the implications of that usage for the Mesa architecture and its implementation. This paper discusses Mesa's byte encoding, patterns of memory references, use of an expression evaluation stack, and the costs of emulating 32-bit operations on a 1 6-bit processor.

A version of this paper appeared in The Proceedings of the Symposium on Programming Languages and Operating Systems, December 1981, Palo Alto California.

CR categories: B.1.5, C.4, D.3.4, D.4.8.

Key words and phrases: architecture, instruction set analysis, microcode emulation, performance analysis.

Xerox Corporation VA Palo Alto Research Centers 3333 Coyote Hill Road
Palo Alto, California

1. Introduction

This paper reports measurements of dynamic instruction frequencies for two Mesa [ 1,21 programs running on a Dorado personal computer [ 5 ] at the Computer Science Laboratory of the Xerox Palo Alto Research Centers. The purpose of this study is to examine the patterns of use associated with the Mesa instruction set' and to find the implications of that usage for the Mesa architecture and its implementation. This paper discusses Mesa's byte encoding, patterns of memory references, use of an expression evaluation stack, and the costs of emulating 32-bit operations on a 16-bit processor.

Mesa is a high level, systems implementation language with a strong, flexible type machinery that permits independently compiled programs to be combined as a functional unit. The Mesa compiler generates instructions that run on any processor that implements the Mesa architecture. The Mesa architecture defines the instruction set and other run time facilities necessary to support Mesa programs. There are a variety of implementations of Mesa, including one for the Dorado. The work described here was done with a prototype version of the Mesa architecture. The differences between the two architectures are not consequential to this study. The official architecture is described elsewhere [ 81.

2. Experimental Method

The author modified the Dorado's microcoded, Mesa emulator to keep statistics on instruction frequencies. The microcode maintained an array of 216 32-bit counters, where each element in

Xerox Corporation Page 1 Jun 01, 1982

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An Analysis of a Mesa Instruction Set

the array contained the count of the number of times a particular pair of instructions executed. The microcode was modified to save the opcode byte of the l...