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Method for MESI encoding to tolerate double-bit errors

IP.com Disclosure Number: IPCOM000128930D
Publication Date: 2005-Sep-21
Document File: 3 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for modified exclusive shared and invalid (MESI) encoding to tolerate double-bit errors. Benefits include improved functionality.

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Method for MESI encoding to tolerate double-bit errors

Disclosed is a method for modified exclusive shared and invalid (MESI) encoding to tolerate double-bit errors. Benefits include improved functionality.

Background

              Conventional processor caches are designed with single-bit error correction with double-bit error detection (SECDED) error checking and correction (ECC) protection to correct single-bit errors and detect double-bit errors in cache tags and data. Process trends indicate that soft errors are likely to increase with next generation processors. Caches must be designed to protect against double-bit errors.

              MESI state encoding is designed to correct single-bit errors in a low level cache. One example of encoding is the assignment of values to errors. The difference between the value of modified (M-state) errors and the value of any other state is 3. Assuming only single-bit errors occur, single-bit M-state errors can be distinguished from single bit errors in non-M states. As a result, single-bit M-state errors can be corrected without interrupting processing. Single-bit errors of non-M states can be detected and the lines can be invalidated.

General description

              The disclosed method provides MESI encoding to handle single-bit or double-bit errors in  MESI states. Future generation processor caches and processors built on a process that is expected to tolerate double-bit errors can benefit from the disclosed method.

              The disclosed method provides preferential treatment to M-state lines. Single-bit or double-bit M-state errors are tolerated. Single-bit errors in non-M states are corrected. Double-bit errors in non-M states are detected. (This method is different from encoding schemes derived from error coding that protect all states from double-bit errors.)

              The disclosed MESI encoding requires 7 bits as compared to 8 bits for an encoding that corrects all states. The disclosed MESIP encoding requires 7 bits as compared to 10 bits for an encoding that corrects all states. With MESIP protocol, the processor firmware drains all the queues and checks if a corrupted line is updated. If the corrupted line is transformed to a valid state, the corruption is to a P-state line, which has been corrected. Otherwise, the line must be invalidated because it is a corrupted E-state, S-state, or I-state line.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to enabling the correction or tolerance of double-bit errors in MESI and some MESIP states without interrupting processing

Detailed description

              The disclosed method is MESI encoding to tolerate doub...