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Method for support on the CPU die for I/O and networking in large-scale CMP systems

IP.com Disclosure Number: IPCOM000128932D
Publication Date: 2005-Sep-21
Document File: 3 page(s) / 18K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for support on the central processor (CPU) die support for input/output (I/O) and networking in large-scale chip multiprocessor (CMP) systems. Benefits include improved functionality and improved performance

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Method for support on the CPU die for I/O and networking in large-scale CMP systems

Disclosed is a method for support on the central processor (CPU) die support for input/output (I/O) and networking in large-scale chip multiprocessor (CMP) systems. Benefits include improved functionality and improved performance.

Background

              The level of network input/output (I/O) integration from conventional devices terminates layer-2 traffic at a discrete platform element, such as a network interface card (NIC) or an I/O hub (IOH). Traffic must traverse the IOH and a memory controller hub (MCH). As a result, the host processor is prevented from performing layer-2 (MAC layer) or layer-1 I/O processing.

              No conventional hardware enables lower-layer I/O to be directly processed on the CPU die.

             

If the data is not processed on-die, the data is moved to memory. If the CMP uses an integrated memory controller (iMC) then I/O traffic may traverse the on-die fabric before being brought back for the application to use or the layer-3 (eg. TCP/IP) processing to take place. As line rates increase to 100 Gbs or more, a significant amount of memory traffic is added. Additionally, large blocks of data from the network are place in coherent memory. The efficient processing of I/O data depends on low-latency paths between the memory hierarchy and the computing elements.

General description

              The disclosed method is highly efficient network and I/O connectivity to a CMP system, such as with 32+ computing cores, by effectively moving some or all of layer-2 and layer-1 processing to the on-CPU die.

              The key elements of the disclosed method include:

•             One or more I/O ports for sending and receiving lower-layer network traffic

•             On-die routing element capable of directing received data to a processing element capable of framing and extracting the data

•             On-die routing element capable of directing data targeted for an external network or other destination to a suitable I/O port

•             One or more on-die processing elements capable of receiving higher-level data from a processing element and constructing the required packet format for the targeted network

•             One or more on-die processing elements capable of processing the network traffic, extracting the higher-level data, and directing it to the right processing element

•             Communication agents associated with each I/O processing element, which are capable of using the on-die fabric

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing on-CPU die I/O and network processing on CMP systems

•             Improved functionality due to providing scalability by enabling more computing elements to be used to process increased networking traffic

•             Improved functionality due to enabling greater control over the scheduling, data movement and processing...