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Method for a realtime CPU state dump cycle for post-silicon debug

IP.com Disclosure Number: IPCOM000128934D
Publication Date: 2005-Sep-21
Document File: 5 page(s) / 131K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a realtime central processing unit (CPU) state dump cycle for post-silicon debug. Benefits include improved functionality, improved performance, improved debug efficiency, an improved test environment, and improved cost effectiveness.

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Method for a realtime CPU state dump cycle for post-silicon debug

Disclosed is a method for a realtime central processing unit (CPU) state dump cycle for post-silicon debug. Benefits include improved functionality, improved performance, improved debug efficiency, an improved test environment, and improved cost effectiveness.

General description

              The disclosed method is a realtime CPU state dump cycle and state restore cycle using on-chip compressed memory. The method is not specific to any class of CPUs. However, if parallel

state dumping is performed on CPU serial links and fully buffered dynamic random access memory (DRAM) (FBD) ports, the method becomes specific to serially interfaced processors. If a test port interface or any special purpose interface provided on socket dumps the state, the method applies to any class of CPUs.

              The key elements of the disclosed method include:

•             State synchronization logic

•             Compression and decompression logic

•             State dump cycle finite state machine (FSM)

Advantages

              The disclosed method provides advantages, including:
•             Improved debug efficiency by decreasing the test suspend time and reproducing the test failure in short time

•             Improved functionality due to enabling the dumping of state information on all available CPU serial links and fully-buffered DRAM (FBD) links if the test is configured appropriately

•             Improved performance due to providing a faster test cycle by requiring only multiple-socket synchronization and quiescence time

•             Improved performance due to enabling test execution and the state dump to occur in parallel if parallel state dump is implemented

•             Improved performance due to suspending the test for a shorter time (order of thousands of clock ticks)

•             Improved reliability due to improving testing

•             Improved test environment due to providing a CPU state dump cycle for large state CPUs

•             Improved test environment due to enabling a test independent way of dumping the state by freezing the system at test failure and dumping the state information captured in compressed memory through a test port

•             Improved test environment due to saving the all cache state, which enables test failures to be easily recreated

•             Improved cost effectiveness due to decreasing the memory requirements by compressing the socket state information

•             Improved cost effectiveness due to providing compressed memory for use by applications after CPU release

•             Improved cost effectiveness by enabling processor debug with less trace capture depth (Cheaper Logic Analyzer)

Detailed description

              The disclosed method includes a realtime central processing unit (CPU) state dump cycle for post-silicon debug. A functional block diagram depicts connectivity of various units in real time state dump logic (see Figure 1).

State synchr...