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Method for a scalable architecture for multi-core and system-on-chip (SoC) semiconductor design and test

IP.com Disclosure Number: IPCOM000128935D
Publication Date: 2005-Sep-21
Document File: 4 page(s) / 23K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a scalable architecture for multiple core (multi-core) and system-on-chip (SoC) semiconductor design and test. Benefits include improved functionality, an improved test environment, and an improved design environment.

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Method for a scalable architecture for multi-core and system-on-chip (SoC) semiconductor design and test

Disclosed is a method for a scalable architecture for multiple core (multi-core) and system-on-chip (SoC) semiconductor design and test. Benefits include improved functionality, an improved test environment, and an improved design environment.

 

Background

              Conventional multi-core design for test (DFT) architectures do not support robust scaling of multiple core or SoC designs. Redesign of the whole architecture is typically required when extra cores are added due to the requirement of redesigning the cores. Additionally, the redesign is required due to the limitations of the conventional DFT architectures associated with the relatively small designs with single cores.

              Most multi-core and SoC designs apply to only a few cores. No compression design is tailored to support robust scaling towards designs with a large number of cores.

              Conventional multi-core and SoC products are typically designed by reusing existing cores and macros. The design for the glue logic and other shared building blocks are created from scratch and incur a relatively large cost and time. As microprocessor and SoC products are integrating more and more core and/or macros together, the cost and complexity are growing.

General description

              The disclosed method is a scalable architecture to support robust multiple core design and test.

              The key elements of the disclosed method include:

•             Interface to a two dimensional array of cores (either homogeneous or heterogeneous cores), which can be easily scaled by adding any number of columns of cores. That interface provides parallel communication links to a column of cores, each of which relays the communication to other cores down the line (along the same row).

•             DFT architecture supports parallel testing of a two dimensional array of cores with limited fan-out.

•             Test compression apparatus supports parallel testing of many cores and debugging of a single core out of a two dimensional array of cores.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing a scalable architecture for multiple core (multi-core) and system-on-chip (SoC) semiconductor design and test

•             Improved functionality due to providing an interface with a tester interface on one side and an internal communication interface to the array of cores

•             Improved test environment due to providing a centralized test access port to a tester

•             Improved test environment due to providing robustness by adding test hooks

•             Improved test environment due to generating test output for debugging a single-core or a single column of cores

Detailed description

              The disclosed method includes architecture for maximizing design reuse and delivering optimized DFT performance...