Browse Prior Art Database

Method for Compound Implicit Branch Instruction for Microprocessors

IP.com Disclosure Number: IPCOM000128936D
Publication Date: 2005-Sep-21
Document File: 6 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for performing a compound implicit branch operation in microprocessors. Benefits include optimized functionality, improved performance and reduced memory latency.

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Method for Compound Implicit Branch Instruction for Microprocessors

Disclosed is a method for performing a compound implicit branch operation in microprocessors. Benefits include optimized functionality, improved performance and reduced memory latency.

Background

             

When a program requires a jump that depends on six different conditions, the programmer must write six conditional checks one after the other with a branch location for each of them. Assuming that only the sixth condition is satisfied, the previous five instructions are fetched, decoded, and executed. The relevant Arithmetic FLAGS are examined. Only when the sixth condition is executed, a branch is performed. The method for compound implicit branch instruction actually enables performing these conditional branches with minimized fetch/decode and memory latency.

General description

The disclosed method includes a branch instruction suitable for microprocessors, including 32-bit, 64-bit, and complex instruction set computer/reduced instruction set computer (CISC/RISC) architectures. Additionally, the execution logic can be applied to microcontrollers, application-specific integrated circuits, and other forms of logic engines that implement logic involving implicit conditions.

The compound implicit branch involves a consolidated jump instruction, a conditional flag register, called the jump flags register (JFR), and an array of reserved memory locations in SRAM/DRAM, called the jump vector table (JVT).

Advantages

              The disclosed method provides advantages, including:


•             Improved functionality due to providing a compound implicit branch instruction

•             Improved functionality due to providing a jump vector table

•             Improved functionality due to providing scalability of the jump instruction set

•             Improved functionality due to providing a RISC implementation for all conditional jumps
•             Improved performance due to improving fetch/decode efficiency by using processing-in-

      memory chip-type memory controllers that support simple memory manipulation functions

•             Improved performance due to improving instruction pipelining efficiency

•             Improved reliability due to reducing the misprediction of branches

Detailed description

The disclosed method provides a very flexible and powerful branch instruction that combines all conditional jump instructions into a single instruction. It improves fetch/decode efficiency and minimizes memory latency when a series of conditional jump instructions are executed in a program. The instruction provides better branch prediction data points to the branch prediction logic in the CPU to improve instruction pipelining efficiency and reduce the misprediction of branches.

 

To achieve fetch minimization, the disclosed method uses processing-in-memory chip-type memory controllers that support simple memory manipulation functions, such as memory movement, populating memory...