Browse Prior Art Database

Method for model-specific register-based cache-line locking

IP.com Disclosure Number: IPCOM000128945D
Publication Date: 2005-Sep-21
Document File: 3 page(s) / 54K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for model-specific register-based cache-line locking. Benefits include improved functionality and improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Method for model-specific register-based cache-line locking

Disclosed is a method for model-specific register-based cache-line locking. Benefits include improved functionality and improved performance.

Background

              During program execution, processor performance can be improved by having critical or frequently used data or code consistently available from a low-latency cache instead of system memory. If this code or data is brought into the processor’s cache, the code or data is not guaranteed to remain in cache unless access is locked by a mechanism that prevents eviction when cache resources are filled. This procedure is termed cache-line locking.

              Some conventional cache-line locking implementations include a no-fill cache mode and use architecturally visible instructions to lock memory references in the cache. The no-fill cache mode provides cache-line locking at a very coarse granularity by locking all lines in the cache when the mode is invoked. At the point that no-fill mode is entered the entire cache effectively becomes static random access memory (SRAM). The cache loses its capability to take advantage of spatial and temporal locality for memory references not resident in the cache at the time that no-fill mode is entered. When cache-line locking is implemented architecturally, instructions are used that fetch the cachelines associated with memory references from memory and pin them in the cache. The cachelines are unlocked by additional instructions.

General description

              The disclosed method is cache-line locking at a cache-line or cache-way granularity, using registers. They are locken, unlock, and lockway. Locken is a read/write REGISTER that controls the locking of allocations to a specific cache. Unlock releases the locks of all lines in the cache. Lockway contains the way that a locked fill is required to enter when the locken REGISTER is set.

              The disclosed method does not require specific instructions in the architecture for locking memory references in a cache.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to implementing cache-line locking in a processor cache using model specific registers, such as locken, unlock, and lockway
•             Improved performance due to enabling locking at a cache line granularity.

Detailed description

              The disclosed method includes three REGISTERs, locken, unlock, and lockway. Locken is a read/write REGISTER that controls the locking of allocations to a specific cache. When this register is set, all fills to the cache are assigned a status so they are locked in their cache location and cannot be replaced by subsequent misses. When this register is cleared, all fills are given a status in whic...