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A Delay-Based PVT Detection Mechanism

IP.com Disclosure Number: IPCOM000128948D
Publication Date: 2005-Sep-21
Document File: 3 page(s) / 85K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a delay monitoring reference circuit, a delay measuring scale, and a mechanism which measures reference circuit delay and generates Process Voltage and Temperature (PVT) code. Benefits include a solution that provides an extra knob for designers to adjust based on a chip’s operating PVT condition.

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A Delay-Based PVT Detection Mechanism

Disclosed is a method that uses a delay monitoring reference circuit, a delay measuring scale, and a mechanism which measures reference circuit delay and generates Process Voltage and Temperature (PVT) code. Benefits include a solution that provides an extra knob for designers to adjust based on a chip’s operating PVT condition.

Background

CMOS circuits are delayed depending on three main parameters: process, supply voltage, and temperature. Variability in manufacturing results in chips that exhibit a range of performance due to variations in device thresholds, oxide thickness, doping profiles, etc. Chip operating conditions also affect performance. Circuit delay depends on supply voltage, and affects the device current and signal swing. Temperature affects the mobility of holes and electrons, and also the transistor’s threshold voltage. The delay of a static CMOS circuit can be approximated by the following equation:

R-comp (i.e. drive impedance compensation) based PVT detection methods are currently used in some places; however impedance compensation is a DC process, which accounts for resistance “R”, but does not account for any capacitance “C”; therefore, the process is inherently inaccurate.

General Description

The disclosed method contains the following elements to create a delay-based PVT detection method:

Reference Circuit

A reference circuit is used for delay monitoring. The reference circuit is a chain of FO4 inverters, since inverter delay tracks the other gate delays, and includes local routing. A sample reference circuit with its delay variations due to process, voltage, and temperature variations is shown in Figure 1. The simulation results show that process variations have the biggest impact on circuit delay, followed by voltage variations, and lastly, temperature. Reference circuits delay variations across the corners shown in Figure 2. The delay is normalized with typical corner delays. The results show -45% to +115% delay variations across the PVT corners.

Delay Measuring Scale

The disclosed method uses a delay measuring scale which is insensitive to PVT variations. One option is to use a clock period (which can be used as one point) or multiple clock periods. This provides a very coarse scale for measur...