Browse Prior Art Database

Fast Settling Voltage Regulator

IP.com Disclosure Number: IPCOM000128954D
Publication Date: 2005-Sep-22
Document File: 4 page(s) / 117K

Publishing Venue

The IP.com Prior Art Database

Abstract

The invention relates to a fast settling and low noise voltage regulator

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FAST SETTLING LOW NOISE VOLTAGE REGULATOR

FIELD OF THE INVENTION

The present invention relates to voltage regulators that can be used in a variety of applications such as integrated electronic circuits for mobile terminals and hearing instruments and other portable electronic devices or electro-acoustical transducer such as condenser microphones. The present voltage regulator circuit is capable of simultaneously provide a fast settling time after power-on and provide a low noise regulated voltage supply.

Figure 1 depicts a well-know prior art voltage regular topology.

VREG

VBAT

RD

C1

VREF

RC filter

-

+

R2

R1

Vfb

feedback network

Figure 1. Voltage Regulator

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VBAT

VFAST

-

CTRL

S1

BANDGAP

REFERENCE

+

VSLOW

D1

D2

VREF

-

Vinm

C1

+

VREG

R2

R1

C1=25 pF

RD1=RD2=400 GOhm

Vfb

Voltages

VBAT

CTRL

VSLOW

VFAST

VREG

Time

settling-time

Filter OFF Filter ON => Low Noise

Figure 2. Improved Voltage Regulator

It is in fact often the case that very stringent requirements are posed for a voltage regulator circuit as far as output noise and power supply rejection are concerned. Therefore all the noise contributions from the various

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circuit blocks must be minimized, including the noise associated with the reference voltage VREF, which is normally generated by or derived from a bandgap reference circuit.

A common prior art approach has been to low pass filter VREF by means of a RC filter according to figure 1. This low pass filter has either been implemented by using external components (typically the capacitor is external) or by integrated components of a monolithic circuit. In the latter case, the RC filter normally occupies a large die area. For good noise suppression, the RC filter time constant needs to be large such as between
0.1 and 10 seconds which often lead to unacceptable long settling time for the regulated output voltage, VREG, unless measures are employed in order to circumvent this problem.

The present invention solves both the noise and settling time problem, by using an approach which meet both ultra-low noise and fast settling time specifications. A schematic diagram of one embodiment of the present invention is shown schematically in Figure 2.

1) A pair of cross-coupled diodes (schematically represented by RD in Figure 2), biased at about 0 Volts, is used in order to achieve a very high dynamic resistance, preferably at least in the order of 1 Giga ohm and more preferably more than10 Giga ohm such as several hundreds Giga Ohms.

2) The cross-coupled diodes are substantially short-circuited at start- up through a low resistan...