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High-Speed Interface Combo Circuits for Multi-Core Microprocessors

IP.com Disclosure Number: IPCOM000128955D
Publication Date: 2005-Sep-22
Document File: 3 page(s) / 48K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that optimizes the supply voltages between cores and caches to improve power performance in future microprocessors. Benefits include a solution that combines level conversion and synchronization, and uses very little static power.

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High-Speed Interface Combo Circuits for Multi-Core Microprocessors

Disclosed is a method that optimizes the supply voltages between cores and caches to improve power performance in future microprocessors. Benefits include a solution that combines level conversion and synchronization, and uses very little static power.

Background

In the near future, interface combo circuits will be used between various cores and cache voltage domains.

General Description

The disclosed method optimizes the supply voltages between cores and caches to improve power performance in future microprocessors. When workload performance needs to be high, multiple cores can operate at a high voltage for maximum performance, while lower-performance workloads can be operated at lower voltages. This allows the microprocessor to operate with better power efficiencies. Figure 1a shows an example of a dual-vcc, single microprocessor.  Figure 1b shows an example of a multi-vcc, multi-core microprocessor. However, when various cores and caches operate at different supply voltages, they must communicate with each other.  These circuits need to be fast for various cache-to-core, core-to-cache, and core-to-core interfaces for a wide variety of input and output supply voltages.

Pass-gate topologies are used in these interface combo circuits to provide the lowest power for an optimized performance, thereby lowering the overall power overhead.  Storage nodes are fully interruptible for high-noise tolerance, and can be made to be half-interrupted or non-interrupt...