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Dynamic Address Enabling for RAM Sub-Threshold Leakage Reduction During Active and Idle Modes

IP.com Disclosure Number: IPCOM000128957D
Publication Date: 2005-Sep-22
Document File: 2 page(s) / 21K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a two-input MUX, a two-input NOR gate, and access-enabled logic to create dynamic address enabling. Benefits include reducing RAM leakage current for both active and idle modes.

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Dynamic Address Enabling for RAM Sub-Threshold Leakage Reduction During Active and Idle Modes

Disclosed is a method that uses a two-input MUX, a two-input NOR gate, and access-enabled logic to create dynamic address enabling. Benefits include reducing RAM leakage current for both active and idle modes.

Background

Current techniques (e.g. sleep transistors, drowsy caches, body biasing, etc.) are only capable of reducing the sub-threshold leakage current during idle mode. At all times in active mode, only one or two addresses out of thousands are accessed in every cycle, and the rest of the bit cells are left to leak. Figure 1 show the conventional architecture (i.e. used in 6T, 8T RAM). The decoded address is connected directly to the bit cell word line.

General Description

The disclosed method uses a two-input MUX, a two-input NOR gate, and access-enabled logic to create dynamic address enabling. The MUX’s inputs are connected to a full VCC source and a low voltage source. The inputs of the NOR gate are connected to the address decoder output and access enable signal, respectively. The NOR gate drives an address (i.e. a row of bit cells).

At all times, all the memory bit cells are sustained using a low voltage to reduce the sub-threshold leakage. When a particular word line/address is accessed, the decoded input address causes the MUX to switch to the full VCC source and fully charge the address VCC for proper read-write operations.

When data is read from the bit cells, th...