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Wide Test Access Port Architecture

IP.com Disclosure Number: IPCOM000128958D
Publication Date: 2005-Sep-22
Document File: 3 page(s) / 34K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an extension to the IEEE 1149.1 Test Access Port (TAP) interface that reduces the tester vector depth for transactions on products that depend on TAP for controlling and exchanging test data with chip Design-for-Test (DFT) features. The benefit of the approach is the reduction in test vector cost.

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Wide

Test

Access

Port

Architecture

Disclosed is a method for an extension to the IEEE 1149.1 Test Access Port (TAP) interface that reduces the tester vector depth for transactions on products that depend on TAP for controlling and exchanging test data with chip Design-for-Test (DFT) features. The benefit of the approach is the reduction in test vector cost.

Background

Although originally intended for board-level interconnection testing through the boundary scan register, the industry has adopted the TAP for accessing pervasive chip-level test and debug features. This simple, yet robust, serial protocol requires minimal design cost, and enjoys support from many industry standard tools.

The advent of SOCs and multi-core CPUs has only increased the need for DFT features for addressing complex test and debug issues. As a result, the data traffic handled by the TAP has grown significantly. In addition to the traditional loading of control and reading of status data, certain DFT features (e.g. Scan, embedded array access) exchange enormous amounts of serial data through the TAP TDI/TDO pins. This repeated exchange of such data in a high-volume manufacturing environment severely impacts both test time and tester vector memory requirements. The problem is particularly acute for low-cost testers, which have limited vector memory.

One solution is to split the internal serial register chains into register chains that can be accessed in parallel from multiple input and output pins. This approach reduces both vector depth and test time. Unfortunately, this approach is cost-prohibitive in design, and loses the simplicity of the serial TAP protocol.

General Description

Figure 1 shows the required components for the disclosed method’s wide-TAP architecture (in red). The parallel-in serial-out (PISO) register picks up several data bits in parallel from the input pins, and feeds them to the internal TDI input of the TAP. Likewise, the serial-in parallel-out register (SIPO) gathers serial output appearing at the TDO pin, and feeds them to the parallel output pins. The tester samples the parallel output pins periodically to recover TDO data several bits in parallel. Both PISO and SIPO registers may either be specially added or shared with...