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Latch that Uses a Different Clock for “1” than for “0” Data

IP.com Disclosure Number: IPCOM000128959D
Publication Date: 2005-Sep-22
Document File: 4 page(s) / 19K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a latch that uses a functionally and/or electrically different clock to release the rising output-data transition, and another for the falling output-data transition. Benefits include improving timing convergence.

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Latch that Uses a Different Clock for “1” than for “0” Data

Disclosed is a method for a latch that uses a functionally and/or electrically different clock to release the rising output-data transition, and another for the falling output-data transition. Benefits include improving timing convergence.

Background

When a signal is transmitted by one clock and received by another, clock skew can occur and cause timing problems, such as races. Race problems can often be fixed by using “de-skewing” flops, which capture a signal using one clock and release it using a different clock, or release it only when both clocks have fired. There are various types of de-skewing flops and latches, each appropriate in different circumstances and none universally superior. For example, many such designs require that both clocks be functionally equivalent, or that the transmitter clock fires whenever the receiver clock does. When this does not happen, the clocks produce functionally-incorrect results.

General Description

The disclosed method creates a latch that uses a functionally and/or electrically different clock to release the rising output-data transition, and another for the falling output-data transition. Debug-related clocks often run when the normal logic has been halted (to enable debug probing), and should be off during normal operation (to conserve power). This makes their clock-gating conditions logically very different from those of the “normal” clocks they interface with. The disclosed method applies to situations where the rising and falling signal edges have different timing requirements. One example is a signal S such that when S rises, the user clock is guaranteed to be on. However, when S falls, the user clock is guaranteed to be off. This type of situation is common around test/debug logic, which must turn user clocks off (e.g. halt normal operation and switch to debug probing) and on (e.g. actually probe the logic) in tight synchrony with test signals. The disclosed method releases the rising edge of S when the user clock rises, while releasing the falling edge when the test clock rises. In general, the disclosed method can be used in many situations where a system is turned on with one clock and turned off with a different clock.

Figure 1 shows the disclosed method clock diagram, assuming that the test clock is on during the entire debug process. The test/debug controller forces the user clock on and off in synchrony, driving the signal S hig...