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Low-Power Test and Debug Signature/Snapshot Cell

IP.com Disclosure Number: IPCOM000128960D
Publication Date: 2005-Sep-22
Document File: 4 page(s) / 74K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that allows SigSnap architectures to be used for enhanced debug and testing. Benefits include a solution that consumes less power than the current state of the art.

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Low-Power Test and Debug Signature/Snapshot Cell

Disclosed is a method that allows SigSnap architectures to be used for enhanced debug and testing. Benefits include a solution that consumes less power than the current state of the art.

Background

The use of sequential elements for taking snap shots and signature capture (i.e. SigSnap) is common in the industry (see Figure 1). However, current designs for SigSnap flops consume significant amounts of power during normal operation, especially if they are observing multiple signal inputs. The following is a summary of one type of SigSnap flop:

§         In snapshot mode, one sets SHIFT=0 and ensures that SERIAL_IN=0. At the desired cycle, SCLK is pulsed once. The signal D (which typically is chosen by the post-silicon team as an “important” signal for capture) is then captured for later observation.

§         In shiftout mode, one sets SHIFT=1 and pulse SCLK continuously. Many of these sequentials are connected in a daisy-chain, with the SERIAL_OUT from one driving the SERIAL_IN of the next. This lets the prior snapshot shift out to the tester. It also clears out the serial chain by shifting in a “0” from the front of the chain.

§         Finally, in signature mode, one sets SHIFT=0 and pulse SCLK continuously. This takes continual snapshots of D. By virtue of the serial chain (and feedback taps, not shown here), it also compresses them into a small signature using LFSR techniques.

§         In normal (non-test) operation, SCLK is off; the main goal is to consume as little power/area as possible.

General Description

One problem is that even with SCLK off, the signal X can easily bounce during normal operations. Unfortunately, while the XOR gates are indispensable for signature compression, their outputs change every time one input changes. To make matters worse, there is a tendency to use multiple-data-input SigSnap flops (see Figure 2).

A single four-input SigSnap flop has four inputs (D1, D2, D3 and D4) instead of just one. This limits its usefulness in taking snapshots. However, there is an obvious reduction in area (one sequential to observe four signals instead of one per signal) and its usefulness in signature capture is reduced only slightly. Unfortunately, the amount of normal-mode power climbs; toggling on the inputs will not only toggle X, but also toggle DD and several internal nodes of a large four-input XOR gate. The disclosed method reduces this unwanted toggling of XOR-related inputs during normal mode. First, the mux is redrawn in a boolean-equivalent manner (see Figure 3).

During normal mode, with SCLK off, the value of SHIFT is insignificant. It is ensured to be “1”, ensuring that any toggling on...